changeset 0e9c904551c1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0e9c904551c1
description:
X86: Add a LocalApic trace flag.
diffstat:
2 files changed, 2 insertions(+)
src/arch/x86/SConscript | 1 +
src/arch/x86/interrupts.cc | 1 +
diffs (35 lines):
diff -r e8abda6e0980 -r 0e9c904551c1 src/arch/x86/SConscript
--- a/src/arch/x86/SConscript Sun Oct 12 11:08:00 2008 -0700
+++ b/src/arch/x86/SConscript Sun Oct 12 12:07:25 2008 -0700
@@ -109,6 +109,8 @@
TraceFlag('X86')
if env['FULL_SYSTEM']:
+ TraceFlag('LocalApic')
+
SimObject('X86LocalApic.py')
SimObject('X86System.py')
diff -r e8abda6e0980 -r 0e9c904551c1 src/arch/x86/interrupts.cc
--- a/src/arch/x86/interrupts.cc Sun Oct 12 11:08:00 2008 -0700
+++ b/src/arch/x86/interrupts.cc Sun Oct 12 12:07:25 2008 -0700
@@ -215,6 +215,9 @@
panic("Accessed more than one register at a time in the APIC!\n");
ApicRegIndex reg = decodeAddr(offset);
uint32_t val = htog(readReg(reg));
+ DPRINTF(LocalApic,
+ "Reading Local APIC register %d at offset %#x as %#x.\n",
+ reg, offset, val);
pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
return latency;
}
@@ -229,6 +232,9 @@
ApicRegIndex reg = decodeAddr(offset);
uint32_t val = regs[reg];
pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
+ DPRINTF(LocalApic,
+ "Writing Local APIC register %d at offset %#x as %#x.\n",
+ reg, offset, gtoh(val));
setReg(reg, gtoh(val));
return latency;
}
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