changeset f548d22a2f71 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f548d22a2f71
description:
X86: Actually use the extra vector bits we get from ICW2.
diffstat:
2 files changed, 2 insertions(+)
src/dev/x86/i8259.cc | 1 +
src/dev/x86/i8259.hh | 1 +
diffs (36 lines):
diff -r 74f76480407f -r f548d22a2f71 src/dev/x86/i8259.cc
--- a/src/dev/x86/i8259.cc Sun Oct 12 13:45:21 2008 -0700
+++ b/src/dev/x86/i8259.cc Sun Oct 12 13:51:48 2008 -0700
@@ -128,8 +128,9 @@
break;
case 0x1:
DPRINTF(I8259, "Received initialization command word 2.\n");
+ vectorOffset = val & ~mask(3);
DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
- val & ~mask(3), val | mask(3));
+ vectorOffset, vectorOffset | mask(3));
if (cascadeMode) {
initControlWord++;
} else {
diff -r 74f76480407f -r f548d22a2f71 src/dev/x86/i8259.hh
--- a/src/dev/x86/i8259.hh Sun Oct 12 13:45:21 2008 -0700
+++ b/src/dev/x86/i8259.hh Sun Oct 12 13:51:48 2008 -0700
@@ -53,6 +53,9 @@
// Interrupt Mask Register
uint8_t IMR;
+ // The higher order bits of the vector to return
+ uint8_t vectorOffset;
+
bool cascadeMode;
// A bit vector of lines with slaves attached, or the slave id, depending
// on if this is a master or slave PIC.
@@ -77,7 +80,7 @@
I8259(Params * p) : BasicPioDevice(p), IntDev(this),
latency(p->pio_latency), output(p->output),
mode(p->mode), IRR(0), ISR(0), IMR(0),
- readIRR(true), initControlWord(0)
+ vectorOffset(0), readIRR(true), initControlWord(0)
{
pioSize = 2;
}
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