changeset f332946e12b2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f332946e12b2
description:
X86: Let segment manipulation microops be conditional.
diffstat:
0 files changed
diffs (12 lines):
diff -r 379f926bc5ff -r f332946e12b2 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Sun Oct 12 20:17:38 2008 -0700
+++ b/src/arch/x86/isa/microops/regop.isa Sun Oct 12 20:25:06 2008 -0700
@@ -978,7 +978,7 @@
'''
# Microops for manipulating segmentation registers
- class SegOp(RegOp):
+ class SegOp(CondRegOp):
abstract = True
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(SegOp, self).__init__(dest, \
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