changeset 6f1cab082ba7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6f1cab082ba7
description:
X86: Add wrval/rdval microops for reading significant miscregs.
diffstat:
3 files changed, 10 insertions(+), 2 deletions(-)
src/arch/x86/isa/microasm.isa | 2 ++
src/arch/x86/isa/microops/regop.isa | 8 ++++++++
src/arch/x86/isa/operands.isa | 2 --
diffs (56 lines):
diff -r 54c2d92f601e -r 6f1cab082ba7 src/arch/x86/isa/microasm.isa
--- a/src/arch/x86/isa/microasm.isa Sun Oct 12 22:42:10 2008 -0700
+++ b/src/arch/x86/isa/microasm.isa Sun Oct 12 22:55:55 2008 -0700
@@ -159,6 +159,11 @@
assembler.symbols["CTrue"] = "ConditionTests::True"
assembler.symbols["CFalse"] = "ConditionTests::False"
+ for reg in ('sysenter_cs', 'sysenter_esp', 'sysenter_eip',
+ 'star', 'lstar', 'cstar', 'sf_mask',
+ 'kernel_gs_base'):
+ assembler.symbols[reg] = "MISCREG_%s" % reg.upper()
+
# Code literal which forces a default 64 bit operand size in 64 bit mode.
assembler.symbols["oszIn64Override"] = '''
if (machInst.mode.submode == SixtyFourBitMode &&
diff -r 54c2d92f601e -r 6f1cab082ba7 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Sun Oct 12 22:42:10 2008 -0700
+++ b/src/arch/x86/isa/microops/regop.isa Sun Oct 12 22:55:55 2008 -0700
@@ -1028,6 +1028,22 @@
DestReg = SegSelSrc1;
'''
+ class Rdval(RegOp):
+ def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+ super(Rdval, self).__init__(dest, \
+ src1, "NUM_INTREGS", flags, dataSize)
+ code = '''
+ DestReg = MiscRegSrc1;
+ '''
+
+ class Wrval(RegOp):
+ def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+ super(Wrval, self).__init__(dest, \
+ src1, "NUM_INTREGS", flags, dataSize)
+ code = '''
+ MiscRegDest = SrcReg1;
+ '''
+
class Chks(RegOp):
def __init__(self, dest, src1, src2=0,
flags=None, dataSize="env.dataSize"):
diff -r 54c2d92f601e -r 6f1cab082ba7 src/arch/x86/isa/operands.isa
--- a/src/arch/x86/isa/operands.isa Sun Oct 12 22:42:10 2008 -0700
+++ b/src/arch/x86/isa/operands.isa Sun Oct 12 22:55:55 2008 -0700
@@ -153,7 +153,9 @@
'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
- 'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None,
['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 209),
- 'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None,
None), 210),
+ 'MiscRegDest': ('ControlReg', 'uqw', 'dest', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
+ 'MiscRegSrc1': ('ControlReg', 'uqw', 'src1', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
+ 'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None,
['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
+ 'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None,
None), 212),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad',
'IsStore'), 300)
}};
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