changeset a55b78e4b6d6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a55b78e4b6d6
description:
X86: Fix the segment setting code in IRET, and make it restore the
flags.
diffstat:
1 file changed, 1 deletion(-)
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
| 1 -
diffs (22 lines):
diff -r 3995b7c2ae86 -r a55b78e4b6d6
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Sun Oct 12 23:00:28 2008 -0700
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Sun Oct 12 23:05:22 2008 -0700
@@ -190,8 +190,8 @@
# This actually updates state which is wrong. It should wait until we know
# we're not going to fault. Unfortunately, that's hard to do.
- wrdl cs, t7, t2
- wrsel cs, t2
+ wrdl ss, t7, t2
+ wrsel ss, t2
###
### From this point downwards, we can't fault. We can update user visible
state.
@@ -224,6 +224,7 @@
# Ignore this for now.
#RFLAGS.v = temp_RFLAGS
+ wrflags t0, t3
# VIF,VIP,IOPL only changed if (old_CPL = 0)
# IF only changed if (old_CPL <= old_RFLAGS.IOPL)
# VM unchanged
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