changeset de7a82f58985 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=de7a82f58985
description:
CPU: Explain why some code is commented out.
diffstat:
1 file changed, 2 insertions(+)
src/cpu/simple/atomic.cc | 2 ++
diffs (14 lines):
diff -r 4bf6f614871b -r de7a82f58985 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Sun Oct 12 23:50:22 2008 -0700
+++ b/src/cpu/simple/atomic.cc Sun Oct 12 23:52:02 2008 -0700
@@ -730,6 +730,10 @@
dcache_access = false; // assume no dcache access
if (!fromRom) {
+ // This is commented out because the predecoder would act like
+ // a tiny cache otherwise. It wouldn't be flushed when needed
+ // like the I cache. It should be flushed, and when that works
+ // this code should be uncommented.
//Fetch more instruction memory if necessary
//if(predecoder.needMoreBytes())
//{
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