changeset 8ba6b8d32aca in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8ba6b8d32aca
description:
Automated merge with ssh://daystrom.m5sim.org//z/repo/m5
diffstat:
2 files changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/interrupts.cc | 1 -
src/dev/x86/i8259.cc | 1 +
diffs (27 lines):
diff -r 88b1d180cec8 -r 8ba6b8d32aca src/arch/x86/interrupts.cc
--- a/src/arch/x86/interrupts.cc Thu Oct 16 14:16:26 2008 -0400
+++ b/src/arch/x86/interrupts.cc Sun Oct 19 22:50:53 2008 -0400
@@ -294,10 +294,9 @@
case 0:
{
TriggerIntMessage message = pkt->get<TriggerIntMessage>();
- uint8_t vector = message.vector;
DPRINTF(LocalApic,
"Got Trigger Interrupt message with vector %#x.\n",
- vector);
+ message.vector);
// Make sure we're really supposed to get this.
assert((message.destMode == 0 && message.destination == id) ||
(bits((int)message.destination, id)));
diff -r 88b1d180cec8 -r 8ba6b8d32aca src/dev/x86/i8259.cc
--- a/src/dev/x86/i8259.cc Thu Oct 16 14:16:26 2008 -0400
+++ b/src/dev/x86/i8259.cc Sun Oct 19 22:50:53 2008 -0400
@@ -31,6 +31,8 @@
#include "base/bitfield.hh"
#include "dev/x86/i82094aa.hh"
#include "dev/x86/i8259.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this),
latency(p->pio_latency), output(p->output),
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