I'm fairly certain you broke the O3 cpu for Alpha FS with this change. The TLB returns an access violation on a superpage access when the palcode does a hwrei to entSys from callpal_callsys. Something is preventing the mode bit from being set and the call reads a stale value resulting in an access. The first mtpr sets the mode bit, however, the fault occurs on the rei even though it shouldn't.
Ali 4519995215872: testsys.switch_cpus T0 : @__bss_start+2199024826436 : call_pal 0x83 : IntAlu : 4519995217041: testsys.switch_cpus T0 : @Call_Pal_Callsys+1 : and r35,8,r24 : IntAlu : D=0x0000000000000008 4519995217041: testsys.switch_cpus T0 : @Call_Pal_Callsys+5 : hw_mfpr IPR(0x153),r22 : IprAccess : D=0xfffffc000790c000 4519995217041: testsys.switch_cpus T0 : @Call_Pal_Callsys+9 : beq r24,0x4721 : IntAlu : 4519995217041: testsys.switch_cpus T0 : @Call_Pal_Callsys+13 : hw_mfpr IPR(0x149),r12 : IprAccess : D=0xfffffc0000311340 4519995217041: testsys.switch_cpus T0 : @Call_Pal_Callsys+17 : hw_mtpr r31,IPR(0x201) : IprAccess : D=0x0000000000000000 4519995217041: testsys.switch_cpus T0 : @Call_Pal_Callsys+21 : hw_mtpr r31,IPR(0x10f) : IprAccess : D=0x0000000000000000 4519995217041: testsys.switch_cpus T0 : @Call_Pal_Callsys+25 : bis r31,r31,r35 : IntAlu : D=0x0000000000000000 4519995217041: testsys.switch_cpus T0 : @Call_Pal_Callsys+29 : hw_mfpr IPR(0x10b),r23 : IprAccess : D=0x0000020000198d58 4519995217208: testsys.switch_cpus T0 : @Call_Pal_Callsys+33 : hw_mtpr r30,IPR(0x152) : IprAccess : D=0x000000011f813b70 4519995217208: testsys.switch_cpus T0 : @Call_Pal_Callsys+37 : lda r30,-48(r22) : IntAlu : D=0xfffffc000790bfd0 4519995217208: testsys.switch_cpus T0 : @Call_Pal_Callsys+41 : stq r29,16(r30) : MemWrite : D=0x00000200002309e0 A=0xfffffc000790bfe0 4519995217208: testsys.switch_cpus T0 : @Call_Pal_Callsys+45 : stq r24,0(r30) : MemWrite : D=0x0000000000000008 A=0xfffffc000790bfd0 4519995217208: testsys.switch_cpus T0 : @Call_Pal_Callsys+49 : stq r23,8(r30) : MemWrite : D=0x0000020000198d58 A=0xfffffc000790bfd8 4519995217208: testsys.switch_cpus T0 : @Call_Pal_Callsys+53 : hw_mtpr r12,IPR(0x10b) : IprAccess : D=0xfffffc0000311340 4519995217208: testsys.switch_cpus T0 : @Call_Pal_Callsys+57 : hw_mfpr IPR(0x156),r29 : IprAccess : D=0xfffffc00007a0900 4519995217208: testsys.switch_cpus T0 : @Call_Pal_Callsys+61 : hw_rei f54 : IntAlu : 4519995401075: testsys.switch_cpus T0 : @Trap_Iaccvio+1 : nop (bis r31,r31,r31) : No_OpClass : 4519995401075: testsys.switch_cpus T0 : @Trap_Iaccvio+5 : sll r35,60,r39 : IntAlu : D=0x0000000000000000 4519995401075: testsys.switch_cpus T0 : @Trap_Iaccvio+9 : hw_mtpr r31,IPR(0x10f) : IprAccess : D=0x0000000000000000 4519995401075: testsys.switch_cpus T0 : @Trap_Iaccvio+13 : bis r35,r31,r36 : IntAlu : D=0x0000000000000000 On Aug 24, 2008, at 8:14 PM, Gabe Black wrote: > I'm making a patch which is supposed to remove hwrei from the cpu > models, and it seems to work. One thing that makes me a little > nervous, > though is that ozone is doing something with locks that the other CPUs > aren't. I was hoping the regressions would help me figure out what the > deal was with that, but I see we don't have any Alpha O3 FS > regressions. > I'm pretty sure I heard that should work, so maybe we should have some > regressions for it? > > Gabe > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
