No regressions break, but any simulation that includes a detailed cpu in alpha fs does.
Ali On Oct 20, 2008, at 12:57 PM, Gabe Black wrote: > I'm in Michigan visiting family at the moment, but when I get back > I'll > fix it. What regression breaks it? I ran all the quick regressions for > every change that affected anything outside of x86, including this > one, > and it worked for me. If I had to take a blind stab at it, I'd say > it's > because the lock flag isn't being cleared in the instruction execute > function like it was in it's previous incarnation, but that's just > from > scanning the diff and guessing. > > Gabe > > Ali Saidi wrote: >> I confirmed that changeset broke full-system alpha o3 simulation. >> Please either fix it or revert the change. >> Ali >> >> On Oct 11, 2008, at 2:35 PM, Gabe Black wrote: >> >> >>> changeset 67cc7f0427e7 in /z/repo/m5 >>> details: http://repo.m5sim.org/m5?cmd=changeset;node=67cc7f0427e7 >>> description: >>> CPU: Eliminate the hwrei function. >>> >>> diffstat: >>> >>> 10 files changed, 4 insertions(+), 46 deletions(-) >>> src/arch/alpha/ev5.cc | 8 -------- >>> src/arch/alpha/isa/decoder.isa | 5 ++++- >>> src/cpu/exec_context.hh | 2 -- >>> src/cpu/o3/cpu.cc | 7 ------- >>> src/cpu/o3/cpu.hh | 1 - >>> src/cpu/o3/dyn_inst.hh | 1 - >>> src/cpu/o3/dyn_inst_impl.hh | 11 ----------- >>> src/cpu/ozone/cpu_impl.hh | 7 ------- >>> src/cpu/ozone/dyn_inst_impl.hh | 7 ------- >>> src/cpu/simple_thread.hh | 1 - >>> >>> diffs (269 lines): >>> >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/arch/alpha/ev5.cc >>> --- a/src/arch/alpha/ev5.cc Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/arch/alpha/ev5.cc Sat Oct 11 02:27:21 2008 -0700 >>> @@ -552,23 +552,6 @@ >>> >>> using namespace AlphaISA; >>> >>> -Fault >>> -SimpleThread::hwrei() >>> -{ >>> - if (!(readPC() & 0x3)) >>> - return new UnimplementedOpcodeFault; >>> - >>> - setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR)); >>> - >>> - if (!misspeculating()) { >>> - if (kernelStats) >>> - kernelStats->hwrei(); >>> - } >>> - >>> - // FIXME: XXX check for interrupts? XXX >>> - return NoFault; >>> -} >>> - >>> /** >>> * Check for special simulator handling of specific PAL calls. >>> * If return value is false, actual PAL call will be suppressed. >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/arch/alpha/isa/decoder.isa >>> --- a/src/arch/alpha/isa/decoder.isa Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/arch/alpha/isa/decoder.isa Sat Oct 11 02:27:21 2008 -0700 >>> @@ -786,7 +786,16 @@ >>> format BasicOperate { >>> 0x1e: decode PALMODE { >>> 0: OpcdecFault::hw_rei(); >>> - 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, >>> IsSerializeBefore); >>> + 1: hw_rei({{ >>> + NPC = ExcAddr; >>> + ThreadContext * tc = xc->tcBase(); >>> + if (!tc->misspeculating()) { >>> + AlphaISA::Kernel::Statistics * kernelStats = >>> + tc->getKernelStats(); >>> + if (kernelStats) >>> + kernelStats->hwrei(); >>> + } >>> + }}, IsSerializing, IsSerializeBefore); >>> } >>> >>> // M5 special opcodes use the reserved 0x01 opcode space >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/arch/alpha/isa/main.isa >>> --- a/src/arch/alpha/isa/main.isa Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/arch/alpha/isa/main.isa Sat Oct 11 02:27:21 2008 -0700 >>> @@ -69,6 +69,7 @@ >>> #include <math.h> >>> >>> #if FULL_SYSTEM >>> +#include "arch/alpha/kernel_stats.hh" >>> #include "sim/pseudo_inst.hh" >>> #endif >>> #include "arch/alpha/ipr.hh" >>> @@ -187,6 +188,7 @@ >>> 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1), >>> 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1), >>> 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1), >>> + 'ExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1), >>> # The next two are hacks for non-full-system call-pal emulation >>> 'R0': ('IntReg', 'uq', '0', None, 1), >>> 'R16': ('IntReg', 'uq', '16', None, 1), >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/checker/cpu.hh >>> --- a/src/cpu/checker/cpu.hh Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/checker/cpu.hh Sat Oct 11 02:27:21 2008 -0700 >>> @@ -336,7 +336,6 @@ >>> void translateDataReadReq(Request *req); >>> >>> #if FULL_SYSTEM >>> - Fault hwrei() { return thread->hwrei(); } >>> void ev5_trap(Fault fault) { fault->invoke(tc); } >>> bool simPalCheck(int palFunc) { return thread- >>> >>>> simPalCheck(palFunc); } >>>> >>> #else >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/exec_context.hh >>> --- a/src/cpu/exec_context.hh Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/exec_context.hh Sat Oct 11 02:27:21 2008 -0700 >>> @@ -144,10 +144,6 @@ >>> void writeHint(Addr addr, int size, unsigned flags); >>> >>> #if FULL_SYSTEM >>> - /** Somewhat Alpha-specific function that handles returning >>> from >>> - * an error or interrupt. */ >>> - Fault hwrei(); >>> - >>> /** >>> * Check for special simulator handling of specific PAL calls. >>> If >>> * return value is false, actual PAL call will be suppressed. >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/o3/cpu.cc >>> --- a/src/cpu/o3/cpu.cc Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/o3/cpu.cc Sat Oct 11 02:27:21 2008 -0700 >>> @@ -903,21 +903,6 @@ >>> DPRINTF(IPI,"Suspended Processor awoke\n"); >>> this->threadContexts[0]->activate(); >>> } >>> -} >>> - >>> -template <class Impl> >>> -Fault >>> -FullO3CPU<Impl>::hwrei(unsigned tid) >>> -{ >>> -#if THE_ISA == ALPHA_ISA >>> - // Need to clear the lock flag upon returning from an >>> interrupt. >>> - this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, >>> tid); >>> - >>> - this->thread[tid]->kernelStats->hwrei(); >>> - >>> - // FIXME: XXX check for interrupts? XXX >>> -#endif >>> - return NoFault; >>> } >>> >>> template <class Impl> >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/o3/cpu.hh >>> --- a/src/cpu/o3/cpu.hh Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/o3/cpu.hh Sat Oct 11 02:27:21 2008 -0700 >>> @@ -414,9 +414,6 @@ >>> /** Posts an interrupt. */ >>> void post_interrupt(int int_num, int index); >>> >>> - /** HW return from error interrupt. */ >>> - Fault hwrei(unsigned tid); >>> - >>> bool simPalCheck(int palFunc, unsigned tid); >>> >>> /** Returns the Fault for any valid interrupt. */ >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/o3/dyn_inst.hh >>> --- a/src/cpu/o3/dyn_inst.hh Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/o3/dyn_inst.hh Sat Oct 11 02:27:21 2008 -0700 >>> @@ -168,8 +168,6 @@ >>> } >>> >>> #if FULL_SYSTEM >>> - /** Calls hardware return from error interrupt. */ >>> - Fault hwrei(); >>> /** Traps to handle specified fault. */ >>> void trap(Fault fault); >>> bool simPalCheck(int palFunc); >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/o3/dyn_inst_impl.hh >>> --- a/src/cpu/o3/dyn_inst_impl.hh Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/o3/dyn_inst_impl.hh Sat Oct 11 02:27:21 2008 -0700 >>> @@ -125,28 +125,6 @@ >>> >>> #if FULL_SYSTEM >>> template <class Impl> >>> -Fault >>> -BaseO3DynInst<Impl>::hwrei() >>> -{ >>> -#if THE_ISA == ALPHA_ISA >>> - // Can only do a hwrei when in pal mode. >>> - if (!(this->readPC() & 0x3)) >>> - return new AlphaISA::UnimplementedOpcodeFault; >>> - >>> - // Set the next PC based on the value of the EXC_ADDR IPR. >>> - this->setNextPC(this->cpu- >>> >>>> readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, >>>> >>> - this->threadNumber)); >>> - >>> - // Tell CPU to clear any state it needs to if a hwrei is taken. >>> - this->cpu->hwrei(this->threadNumber); >>> -#else >>> - >>> -#endif >>> - // FIXME: XXX check for interrupts? XXX >>> - return NoFault; >>> -} >>> - >>> -template <class Impl> >>> void >>> BaseO3DynInst<Impl>::trap(Fault fault) >>> { >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/ozone/cpu.hh >>> --- a/src/cpu/ozone/cpu.hh Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/ozone/cpu.hh Sat Oct 11 02:27:21 2008 -0700 >>> @@ -510,7 +510,6 @@ >>> void dumpInsts() { frontEnd->dumpInsts(); } >>> >>> #if FULL_SYSTEM >>> - Fault hwrei(); >>> bool simPalCheck(int palFunc); >>> void processInterrupts(); >>> #else >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/ozone/cpu_impl.hh >>> --- a/src/cpu/ozone/cpu_impl.hh Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/ozone/cpu_impl.hh Sat Oct 11 02:27:21 2008 -0700 >>> @@ -669,21 +669,6 @@ >>> } >>> #else >>> template <class Impl> >>> -Fault >>> -OzoneCPU<Impl>::hwrei() >>> -{ >>> - // Need to move this to ISA code >>> - // May also need to make this per thread >>> - >>> - lockFlag = false; >>> - lockAddrList.clear(); >>> - thread.kernelStats->hwrei(); >>> - >>> - // FIXME: XXX check for interrupts? XXX >>> - return NoFault; >>> -} >>> - >>> -template <class Impl> >>> void >>> OzoneCPU<Impl>::processInterrupts() >>> { >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/ozone/dyn_inst.hh >>> --- a/src/cpu/ozone/dyn_inst.hh Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/ozone/dyn_inst.hh Sat Oct 11 02:27:21 2008 -0700 >>> @@ -240,7 +240,6 @@ >>> void setMiscReg(int misc_reg, const MiscReg &val); >>> >>> #if FULL_SYSTEM >>> - Fault hwrei(); >>> void trap(Fault fault); >>> bool simPalCheck(int palFunc); >>> #else >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/ozone/dyn_inst_impl.hh >>> --- a/src/cpu/ozone/dyn_inst_impl.hh Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/ozone/dyn_inst_impl.hh Sat Oct 11 02:27:21 2008 -0700 >>> @@ -249,21 +249,6 @@ >>> #if FULL_SYSTEM >>> >>> template <class Impl> >>> -Fault >>> -OzoneDynInst<Impl>::hwrei() >>> -{ >>> - if (!(this->readPC() & 0x3)) >>> - return new AlphaISA::UnimplementedOpcodeFault; >>> - >>> - this->setNextPC(this->thread- >>> >>>> readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR)); >>>> >>> - >>> - this->cpu->hwrei(); >>> - >>> - // FIXME: XXX check for interrupts? XXX >>> - return NoFault; >>> -} >>> - >>> -template <class Impl> >>> void >>> OzoneDynInst<Impl>::trap(Fault fault) >>> { >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/simple/base.hh >>> --- a/src/cpu/simple/base.hh Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/simple/base.hh Sat Oct 11 02:27:21 2008 -0700 >>> @@ -413,7 +413,6 @@ >>> //Fault CacheOp(uint8_t Op, Addr EA); >>> >>> #if FULL_SYSTEM >>> - Fault hwrei() { return thread->hwrei(); } >>> void ev5_trap(Fault fault) { fault->invoke(tc); } >>> bool simPalCheck(int palFunc) { return thread- >>> >>>> simPalCheck(palFunc); } >>>> >>> #else >>> diff -r dc073dc6358b -r 67cc7f0427e7 src/cpu/simple_thread.hh >>> --- a/src/cpu/simple_thread.hh Sat Oct 11 02:23:40 2008 -0700 >>> +++ b/src/cpu/simple_thread.hh Sat Oct 11 02:27:21 2008 -0700 >>> @@ -184,8 +184,6 @@ >>> int getDataAsid() { return regs.dataAsid(); } >>> >>> void dumpFuncProfile(); >>> - >>> - Fault hwrei(); >>> >>> bool simPalCheck(int palFunc); >>> >>> _______________________________________________ >>> m5-dev mailing list >>> [email protected] >>> http://m5sim.org/mailman/listinfo/m5-dev >>> >>> >> >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
