changeset bf84e2fa05f7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bf84e2fa05f7
description:
O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU.
Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM
register is updated in a call pal
call sys and thus the translation fails because the user is attempting
to access a super page address.
Minimally, it seems as though some sort of fetch stall or refetch after
a hwrei is required. I think
this works currently because the hwrei uses the exec context interface,
and the o3 stalls when that occurs.
Additionally, these changes don't update the LOCK register and probably
break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only
remove the hwrei change.
diffstat:
16 files changed, 78 insertions(+), 17 deletions(-)
src/arch/alpha/ev5.cc | 23 +++++++++++++++++++++++
src/arch/alpha/isa/decoder.isa | 11 -----------
src/arch/alpha/isa/main.isa | 1 -
src/arch/x86/bios/IntelMP.py | 4 ----
src/cpu/checker/cpu.hh | 1 +
src/cpu/exec_context.hh | 6 +++++-
src/cpu/o3/cpu.cc | 2 ++
src/cpu/o3/cpu.hh | 2 ++
src/cpu/o3/dyn_inst.hh | 2 ++
src/cpu/o3/dyn_inst_impl.hh | 18 ++++++++++++++++++
src/cpu/ozone/cpu.hh | 1 +
src/cpu/ozone/cpu_impl.hh | 7 +++++++
src/cpu/ozone/dyn_inst.hh | 1 +
src/cpu/ozone/dyn_inst_impl.hh | 13 +++++++++++++
src/cpu/simple/base.hh | 1 +
src/cpu/simple_thread.hh | 2 ++
diffs (truncated from 465 to 300 lines):
diff -r 8ba6b8d32aca -r bf84e2fa05f7 src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Sun Oct 19 22:50:53 2008 -0400
+++ b/src/arch/alpha/ev5.cc Mon Oct 20 16:22:59 2008 -0400
@@ -547,3 +547,53 @@
}
} // namespace AlphaISA
+
+#if FULL_SYSTEM
+
+using namespace AlphaISA;
+
+Fault
+SimpleThread::hwrei()
+{
+ if (!(readPC() & 0x3))
+ return new UnimplementedOpcodeFault;
+
+ setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
+
+ if (!misspeculating()) {
+ if (kernelStats)
+ kernelStats->hwrei();
+ }
+
+ // FIXME: XXX check for interrupts? XXX
+ return NoFault;
+}
+
+/**
+ * Check for special simulator handling of specific PAL calls.
+ * If return value is false, actual PAL call will be suppressed.
+ */
+bool
+SimpleThread::simPalCheck(int palFunc)
+{
+ if (kernelStats)
+ kernelStats->callpal(palFunc, tc);
+
+ switch (palFunc) {
+ case PAL::halt:
+ halt();
+ if (--System::numSystemsRunning == 0)
+ exitSimLoop("all cpus halted");
+ break;
+
+ case PAL::bpt:
+ case PAL::bugchk:
+ if (system->breakpoint())
+ return false;
+ break;
+ }
+
+ return true;
+}
+
+#endif // FULL_SYSTEM
diff -r 8ba6b8d32aca -r bf84e2fa05f7 src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Sun Oct 19 22:50:53 2008 -0400
+++ b/src/arch/alpha/isa/decoder.isa Mon Oct 20 16:22:59 2008 -0400
@@ -698,28 +698,7 @@
else {
// check to see if simulator wants to do something special
// on this PAL call (including maybe suppress it)
-
- bool dopal = true;
-
- ThreadContext * tc = xc->tcBase();
- AlphaISA::Kernel::Statistics * kernelStats = tc->getKernelStats();
- System * system = tc->getSystemPtr();
- if (kernelStats)
- kernelStats->callpal(palFunc, tc);
-
- switch (palFunc) {
- case PAL::halt:
- tc->halt();
- if (--System::numSystemsRunning == 0)
- exitSimLoop("all cpus halted");
- break;
-
- case PAL::bpt:
- case PAL::bugchk:
- if (system->breakpoint())
- dopal = false;
- break;
- }
+ bool dopal = xc->simPalCheck(palFunc);
if (dopal) {
xc->setMiscReg(IPR_EXC_ADDR, NPC);
@@ -807,16 +786,7 @@
format BasicOperate {
0x1e: decode PALMODE {
0: OpcdecFault::hw_rei();
- 1: hw_rei({{
- NPC = ExcAddr;
- ThreadContext * tc = xc->tcBase();
- if (!tc->misspeculating()) {
- AlphaISA::Kernel::Statistics * kernelStats =
- tc->getKernelStats();
- if (kernelStats)
- kernelStats->hwrei();
- }
- }}, IsSerializing, IsSerializeBefore);
+ 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
}
// M5 special opcodes use the reserved 0x01 opcode space
diff -r 8ba6b8d32aca -r bf84e2fa05f7 src/arch/alpha/isa/main.isa
--- a/src/arch/alpha/isa/main.isa Sun Oct 19 22:50:53 2008 -0400
+++ b/src/arch/alpha/isa/main.isa Mon Oct 20 16:22:59 2008 -0400
@@ -69,8 +69,6 @@
#include <math.h>
#if FULL_SYSTEM
-#include "arch/alpha/kernel_stats.hh"
-#include "arch/alpha/osfpal.hh"
#include "sim/pseudo_inst.hh"
#endif
#include "arch/alpha/ipr.hh"
@@ -189,7 +187,6 @@
'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
- 'ExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1),
diff -r 8ba6b8d32aca -r bf84e2fa05f7 src/arch/x86/bios/IntelMP.py
--- a/src/arch/x86/bios/IntelMP.py Sun Oct 19 22:50:53 2008 -0400
+++ b/src/arch/x86/bios/IntelMP.py Mon Oct 20 16:22:59 2008 -0400
@@ -85,15 +85,6 @@
ext_entries = VectorParam.X86IntelMPExtConfigEntry([],
'extended configuration table entries')
-
- def add_entry(self, entry):
- if isinstance(entry, X86IntelMPBaseConfigEntry):
- self.base_entries.append(entry)
- elif isinstance(entry, X86IntelMPExtConfigEntry):
- self.base_entries.append(entry)
- else:
- panic("Don't know what type of Intel MP entry %s is." \
- % entry.__class__.__name__)
class X86IntelMPBaseConfigEntry(SimObject):
type = 'X86IntelMPBaseConfigEntry'
diff -r 8ba6b8d32aca -r bf84e2fa05f7 src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh Sun Oct 19 22:50:53 2008 -0400
+++ b/src/cpu/checker/cpu.hh Mon Oct 20 16:22:59 2008 -0400
@@ -336,7 +336,9 @@
void translateDataReadReq(Request *req);
#if FULL_SYSTEM
+ Fault hwrei() { return thread->hwrei(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }
+ bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
#else
// Assume that the normal CPU's call to syscall was successful.
// The checker's state would have already been updated by the syscall.
diff -r 8ba6b8d32aca -r bf84e2fa05f7 src/cpu/exec_context.hh
--- a/src/cpu/exec_context.hh Sun Oct 19 22:50:53 2008 -0400
+++ b/src/cpu/exec_context.hh Mon Oct 20 16:22:59 2008 -0400
@@ -143,7 +143,17 @@
* given flags. */
void writeHint(Addr addr, int size, unsigned flags);
-#if !FULL_SYSTEM
+#if FULL_SYSTEM
+ /** Somewhat Alpha-specific function that handles returning from
+ * an error or interrupt. */
+ Fault hwrei();
+
+ /**
+ * Check for special simulator handling of specific PAL calls. If
+ * return value is false, actual PAL call will be suppressed.
+ */
+ bool simPalCheck(int palFunc);
+#else
/** Executes a syscall specified by the callnum. */
void syscall(int64_t callnum);
#endif
diff -r 8ba6b8d32aca -r bf84e2fa05f7 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Sun Oct 19 22:50:53 2008 -0400
+++ b/src/cpu/o3/cpu.cc Mon Oct 20 16:22:59 2008 -0400
@@ -51,6 +51,10 @@
#if USE_CHECKER
#include "cpu/checker/cpu.hh"
+#endif
+
+#if THE_ISA == ALPHA_ISA
+#include "arch/alpha/osfpal.hh"
#endif
class BaseCPUParams;
@@ -899,6 +903,47 @@
DPRINTF(IPI,"Suspended Processor awoke\n");
this->threadContexts[0]->activate();
}
+}
+
+template <class Impl>
+Fault
+FullO3CPU<Impl>::hwrei(unsigned tid)
+{
+#if THE_ISA == ALPHA_ISA
+ // Need to clear the lock flag upon returning from an interrupt.
+ this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
+
+ this->thread[tid]->kernelStats->hwrei();
+
+ // FIXME: XXX check for interrupts? XXX
+#endif
+ return NoFault;
+}
+
+template <class Impl>
+bool
+FullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
+{
+#if THE_ISA == ALPHA_ISA
+ if (this->thread[tid]->kernelStats)
+ this->thread[tid]->kernelStats->callpal(palFunc,
+ this->threadContexts[tid]);
+
+ switch (palFunc) {
+ case PAL::halt:
+ halt();
+ if (--System::numSystemsRunning == 0)
+ exitSimLoop("all cpus halted");
+ break;
+
+ case PAL::bpt:
+ case PAL::bugchk:
+ if (this->system->breakpoint())
+ return false;
+ break;
+ }
+#endif
+ return true;
}
template <class Impl>
diff -r 8ba6b8d32aca -r bf84e2fa05f7 src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh Sun Oct 19 22:50:53 2008 -0400
+++ b/src/cpu/o3/cpu.hh Mon Oct 20 16:22:59 2008 -0400
@@ -414,6 +414,11 @@
/** Posts an interrupt. */
void post_interrupt(int int_num, int index);
+ /** HW return from error interrupt. */
+ Fault hwrei(unsigned tid);
+
+ bool simPalCheck(int palFunc, unsigned tid);
+
/** Returns the Fault for any valid interrupt. */
Fault getInterrupts();
diff -r 8ba6b8d32aca -r bf84e2fa05f7 src/cpu/o3/dyn_inst.hh
--- a/src/cpu/o3/dyn_inst.hh Sun Oct 19 22:50:53 2008 -0400
+++ b/src/cpu/o3/dyn_inst.hh Mon Oct 20 16:22:59 2008 -0400
@@ -168,8 +168,11 @@
}
#if FULL_SYSTEM
+ /** Calls hardware return from error interrupt. */
+ Fault hwrei();
/** Traps to handle specified fault. */
void trap(Fault fault);
+ bool simPalCheck(int palFunc);
#else
/** Calls a syscall. */
void syscall(int64_t callnum);
diff -r 8ba6b8d32aca -r bf84e2fa05f7 src/cpu/o3/dyn_inst_impl.hh
--- a/src/cpu/o3/dyn_inst_impl.hh Sun Oct 19 22:50:53 2008 -0400
+++ b/src/cpu/o3/dyn_inst_impl.hh Mon Oct 20 16:22:59 2008 -0400
@@ -125,10 +125,42 @@
#if FULL_SYSTEM
template <class Impl>
+Fault
+BaseO3DynInst<Impl>::hwrei()
+{
+#if THE_ISA == ALPHA_ISA
+ // Can only do a hwrei when in pal mode.
+ if (!(this->readPC() & 0x3))
+ return new AlphaISA::UnimplementedOpcodeFault;
+
+ // Set the next PC based on the value of the EXC_ADDR IPR.
+ this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
+ this->threadNumber));
+
+ // Tell CPU to clear any state it needs to if a hwrei is taken.
+ this->cpu->hwrei(this->threadNumber);
+#else
+
+#endif
+ // FIXME: XXX check for interrupts? XXX
+ return NoFault;
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
