[m5-dev] [PATCH 1 of 3] X86: Make the timing simple CPU handle variable length instructions

[gblack]

# HG changeset patch
# User Gabe Black <[EMAIL PROTECTED]>
# Date 1226041356 28800
# Node ID 94ef4905a939b782105ce0ebb3c063451744fb3d
# Parent  61c838ecc2259cd0d60dc7d7b9bf0e92cb1a89da
X86: Make the timing simple CPU handle variable length instructions.

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -561,7 +561,8 @@
 void
 TimingSimpleCPU::advanceInst(Fault fault)
 {
-    advancePC(fault);
+    if (fault != NoFault || !stayAtPC)
+        advancePC(fault);
 
     if (_status == Running) {
         // kick off fetch of next instruction... callback from icache
@@ -599,7 +600,8 @@
     }
 
     preExecute();
-    if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
+    if (curStaticInst &&
+            curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
         // load or store: just send to dcache
         Fault fault = curStaticInst->initiateAcc(this, traceData);
         if (_status != Running) {
@@ -638,7 +640,7 @@
                 instCnt++;
             advanceInst(fault);
         }
-    } else {
+    } else if (curStaticInst) {
         // non-memory instruction: execute completely now
         Fault fault = curStaticInst->execute(this, traceData);
 
@@ -657,6 +659,8 @@
                     curStaticInst->isFirstMicroop()))
             instCnt++;
         advanceInst(fault);
+    } else {
+        advanceInst(NoFault);
     }
 
     if (pkt) {
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