Ah, ok. I see where I was getting confused. There doesn't look like there's any way to disable a BAR or force it to a particular value, correct? In reality you wouldn't force a BAR to a particular value you'd just work without it, but that way the existing models won't have to be changed.
Gabe Quoting Ali Saidi <[EMAIL PROTECTED]>: > You should setup the BARs and the BAR sizes with the BARX and BARSizeX > variables. If you set the BAR to 0x1 and the size to 1024, then you > would get an 1024 byte I/O space when Linux reads the bar type, writes > -1 to read the bar size, and then properly configures the device. > > Ali > > > > On Nov 24, 2008, at 9:50 PM, Gabe Black wrote: > > > I dug around in the lspci source a bit, and "[virtual]" means that the > > OS has assigned a resource to a device but it doesn't appear in the > > BARs. It shows up as the memory type because bit 0 of an > > "unimplemented" > > BAR is 0, but the address it prints is what the OS reports which > > matches > > with the legacy addresses. "[disabled]" shows up because the command > > registers memory bit is 0, again because lspci is misinterpreting the > > virtual regions as memory instead of IO. The final region of IO I'm > > assuming is the BMI region in our controller model, and it -is- > > actually > > set up with its BAR. > > > > So the unresolved issue here is still how do I get M5 to do this? I > > need > > to be able to set up an IO BAR and to disable any particular BAR and > > force an address in its place. If there's already a way to do this > > then > > please let me know. If not, I'll go ahead and cook one up. > > > > Gabe > > > > Gabe Black wrote: > >> I've been looking at the implementation of the PCI BAR registers, > >> and I can't see how it's possible to set up an IO decoder. The lowest > >> bit of the BAR is supposed to be a 1 for IO addresses, and the BARs > >> are > >> memset to 0 in the constructor. The only way to set them that I see > >> is > >> to write to the BARs, but that preserves what type it is so it can > >> never > >> change from memory to IO. Also, the thing that sets the range for the > >> various devices just uses the address directly without masking that > >> bit > >> out. What it should do is mask it out, and if it was a 1 transform > >> the > >> rest to an IO address somehow. Also, there doesn't seem to be any > >> way to > >> disable BARs, or at least not that I see. I have the mindshare PCI > >> book, > >> and it says that for legacy IO decoders, like what I'm trying to > >> get to > >> work, the BAR is not implemented. I think that means reading it > >> returns > >> 0, but that part is a little fuzzy. The configuration software is > >> supposed to then recognize that this is a legacy device and turn on > >> it's > >> IO decoders in the command register. There doesn't seem to be any > >> way to > >> set this sort of thing up in the IDE controller, although that's > >> pretty > >> understandable since Alpha probably doesn't expect devices to end > >> up in > >> fixed locations. On my system my IDE controller shows up under > >> lspci as > >> copied below. I'm not sure how to interpret all of it, but the > >> "Memory" > >> regions actually correspond to the IO locations the legacy > >> controllers > >> are supposed to be at. They're marked as "[disabled]" which matches > >> the > >> description of the legacy devices, but I don't know how it determined > >> that. They're also marked as "[virtual]" and I have no idea what that > >> means either, unless it has something to do with an IO MMU. > >> > >> 00:0d.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) (prog- > >> if 8a > >> [Master SecP PriP]) > >> Subsystem: nVidia Corporation Device c55e > >> Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- > >> ParErr- Stepping- SERR- FastB2B- DisINTx- > >> Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- > >> <TAbort- <MAbort- >SERR- <PERR- INTx- > >> Latency: 0 (750ns min, 250ns max) > >> Region 0: [virtual] Memory at 000001f0 (32-bit, > >> non-prefetchable) [disabled] [size=8] > >> Region 1: [virtual] Memory at 000003f0 (type 3, > >> non-prefetchable) [disabled] [size=1] > >> Region 2: [virtual] Memory at 00000170 (32-bit, > >> non-prefetchable) [disabled] [size=8] > >> Region 3: [virtual] Memory at 00000370 (type 3, > >> non-prefetchable) [disabled] [size=1] > >> Region 4: I/O ports at ec00 [size=16] > >> Capabilities: [44] Power Management version 2 > >> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA > >> PME(D0-,D1-,D2-,D3hot-,D3cold-) > >> Status: D0 PME-Enable- DSel=0 DScale=0 PME- > >> Kernel driver in use: AMD_IDE > >> > >> _______________________________________________ > >> m5-dev mailing list > >> m5-dev@m5sim.org > >> http://m5sim.org/mailman/listinfo/m5-dev > >> > > > > _______________________________________________ > > m5-dev mailing list > > m5-dev@m5sim.org > > http://m5sim.org/mailman/listinfo/m5-dev > > > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
