Hi Clint, Did you get anywhere with this?
Nate On Sun, Nov 16, 2008 at 1:23 PM, Clint Smullen <[EMAIL PROTECTED]> wrote: > Heh, disabling this assertion has a similar result as seen in the > fetch unit: the outstanding requests arrive at the simple CPU that > takes over next, and it promptly dies. I'll see if I can come up with > a fix for that, but if someone has any suggestions, t'would be > appreciated. > > - Clint > > On Nov 16, 2008, at 3:40 PM, Clint Smullen wrote: > >> As with the fetch unit, the IEW does not actively do anything to >> prevent switchout until it is fully drained. I am hitting the >> assertion on line 239 of lsq_unit_impl.hh which says "assert(! >> loadQueue[i])". The immediately following line says "loadQueue[i] = >> NULL". Correctness wise, it should not be an issue to just clear >> everything in the load-queue, particularly since they merely point >> to DynInst's, but is there some other reason that this assertion is >> there, or can I just comment it out? >> >> - Clint > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
