i would imagine you need to do patch -p1, not -p0. what errors do you get
when your patching fails?
lisa
On Sun, Nov 30, 2008 at 4:25 PM, Korey Sewell <[EMAIL PROTECTED]> wrote:
> i'm having a problem with my repository as I was trying to fix a bug
> that was stalling Mixie...
>
> basically, i started a new patch but then pulled in the current sets.
> When i tried to merge everything just got screwed up.
>
> So, I just started to clone a fresh repo and apply the patches one at
> a time (With "patch -p0 < ..." command), but that isnt working...
>
> Thus, yes the current stuff is the most recent but I'm stuck until I
> give another look at getting my mercurial repo back to being sane.
>
> On Sun, Nov 30, 2008 at 1:21 PM, nathan binkert <[EMAIL PROTECTED]> wrote:
> > Ok, what's the status now? I can dedicate some time to looking at
> > this now. Are the patches sent out last week the most up to date?
> >
> > Nate
> >
> > On Tue, Nov 25, 2008 at 3:45 PM, Gabe Black <[EMAIL PROTECTED]>
> wrote:
> >> Ok, that sounds good. I didn't look in the second patch or the first one
> >> very closely. Please let me know when/if you're queue is in a
> >> repository. I've had my pending x86 patches on m5sim.org for a while
> now
> >> if you want to see an example, although I don't think they show up in
> >> the web interface.
> >>
> >> Gabe
> >>
> >> Korey Sewell wrote:
> >>> If you get a chance, look at that closely.
> >>>
> >>> I do derive a new tracer from the default tracer (mixie_trace.hh/cc).
> >>>
> >>> What's new is that I'm adding the option for per-stage tracing. To do
> >>> this, the dump function needs to print out the ticks differently as
> >>> there are now an arbitrary amount of stages.
> >>>
> >>> That's why I virtualized a printTicks() function which simply prints
> >>> the commit stage # in the general case, but if you turn stage-tracing
> >>> on for the Mixie it will print out on what cycle a instruction
> >>> finished a particular stage.
> >>>
> >>> On Tue, Nov 25, 2008 at 10:17 PM, <[EMAIL PROTECTED]> wrote:
> >>>
> >>>> There's one other thing I just realized. I'm assuming you're extending
> the trace
> >>>> stuff by modifying exetrace.cc. The idea there was that you could make
> your own
> >>>> class which replaces or inherits from the default tracer, and then set
> that up
> >>>> to run in an arbitrary CPU. In the python, you could then override the
> default
> >>>> tracer your CPU class uses to be the one that does whatever special
> thing you
> >>>> want. The class that keeps track of the execution of a particular
> instruction
> >>>> is extensible as well if you want to add new fields, etc.
> >>>>
> >>>> Gabe
> >>>>
> >>>> Quoting Korey Sewell <[EMAIL PROTECTED]>:
> >>>>
> >>>>
> >>>>> # HG changeset patch
> >>>>> # User Korey Sewell <[EMAIL PROTECTED]>
> >>>>> # Date 1227320916 18000
> >>>>> # Node ID b2b20a241e923c43a6978ea42fab9be4ead71220
> >>>>> # Parent 6f9923f77ced7b25a7a573549fd4ca1b0a49c466
> >>>>> [mq]: make_mixie_cmdline_runnable
> >>>>>
> >>>>> diff -r 6f9923f77ced -r b2b20a241e92 configs/common/Options.py
> >>>>> --- a/configs/common/Options.py Tue Nov 18 16:03:31 2008 -0500
> >>>>> +++ b/configs/common/Options.py Fri Nov 21 21:28:36 2008 -0500
> >>>>> @@ -29,6 +29,7 @@
> >>>>> # system options
> >>>>> parser.add_option("-d", "--detailed", action="store_true")
> >>>>> parser.add_option("-t", "--timing", action="store_true")
> >>>>> +parser.add_option("--mixie", action="store_true")
> >>>>> parser.add_option("-n", "--num-cpus", type="int", default=1)
> >>>>> parser.add_option("--caches", action="store_true")
> >>>>> parser.add_option("--l2cache", action="store_true")
> >>>>> diff -r 6f9923f77ced -r b2b20a241e92 configs/common/Simulation.py
> >>>>> --- a/configs/common/Simulation.py Tue Nov 18 16:03:31 2008 -0500
> >>>>> +++ b/configs/common/Simulation.py Fri Nov 21 21:28:36 2008 -0500
> >>>>> @@ -43,6 +43,11 @@ def setCPUClass(options):
> >>>>> print "O3 CPU must be used with caches"
> >>>>> sys.exit(1)
> >>>>> class TmpClass(DerivO3CPU): pass
> >>>>> + elif options.mixie:
> >>>>> + if not options.caches:
> >>>>> + print "Mixie CPU must be used with caches"
> >>>>> + sys.exit(1)
> >>>>> + class TmpClass(MixieCPU): pass
> >>>>> else:
> >>>>> class TmpClass(AtomicSimpleCPU): pass
> >>>>> atomic = True
> >>>>> diff -r 6f9923f77ced -r b2b20a241e92 src/arch/mips/faults.cc
> >>>>> --- a/src/arch/mips/faults.cc Tue Nov 18 16:03:31 2008 -0500
> >>>>> +++ b/src/arch/mips/faults.cc Fri Nov 21 21:28:36 2008 -0500
> >>>>> @@ -461,6 +461,9 @@ void ResetFault::invoke(ThreadContext *t
> >>>>> tc->setNextPC(vect()+sizeof(MachInst));
> >>>>> tc->setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
> >>>>> DPRINTF(MipsPRA,"(%x) - ResetFault::invoke : PC set to
> >>>>> %x",(unsigned)tc,(unsigned)tc->readPC());
> >>>>> +#else
> >>>>> + //MixieCPU *cpu_ptr =
> reinterpret_cast<MixieCPU*>(tc->getCpuPtr());
> >>>>> + //cpu_ptr->miscRegFile.reset();
> >>>>> #endif
> >>>>>
> >>>>> // Set Coprocessor 1 (Floating Point) To Usable
> >>>>> diff -r 6f9923f77ced -r b2b20a241e92 src/arch/mips/mt.hh
> >>>>> --- a/src/arch/mips/mt.hh Tue Nov 18 16:03:31 2008 -0500
> >>>>> +++ b/src/arch/mips/mt.hh Fri Nov 21 21:28:36 2008 -0500
> >>>>> @@ -68,7 +68,7 @@ getTargetThread(TC *tc)
> >>>>> }
> >>>>>
> >>>>> template <class TC>
> >>>>> -inline void
> >>>>> +void
> >>>>> haltThread(TC *tc)
> >>>>> {
> >>>>> if (tc->status() == TC::Active) {
> >>>>> @@ -77,6 +77,8 @@ haltThread(TC *tc)
> >>>>> // Save last known PC in TCRestart
> >>>>> // @TODO: Needs to check if this is a branch and if so, take
> >>>>> previous instruction
> >>>>> tc->setMiscReg(TCRestart, tc->readNextPC());
> >>>>> +
> >>>>> + //assert(0);
> >>>>>
> >>>>> warn("%i: Halting thread %i in %s @ PC %x, setting restart
> PC to
> >>>>> %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
> >>>>> tc->readPC(), tc->readNextPC());
> >>>>> diff -r 6f9923f77ced -r b2b20a241e92
> src/arch/mips/regfile/misc_regfile.cc
> >>>>> --- a/src/arch/mips/regfile/misc_regfile.cc Tue Nov 18 16:03:31
> 2008 -0500
> >>>>> +++ b/src/arch/mips/regfile/misc_regfile.cc Fri Nov 21 21:28:36
> 2008 -0500
> >>>>> @@ -179,8 +179,10 @@ int MiscRegFile:: getDataAsid()
> >>>>> }
> >>>>> //@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
> >>>>> void
> >>>>> -MiscRegFile::reset(std::string core_name, unsigned num_threads,
> >>>>> - unsigned num_vpes, BaseCPU *_cpu)
> >>>>> +MiscRegFile::reset(std::string core_name,
> >>>>> + unsigned num_threads,
> >>>>> + unsigned num_vpes,
> >>>>> + BaseCPU *_cpu)
> >>>>> {
> >>>>> DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i
> VPEs\n",
> >>>>> num_threads, num_vpes);
> >>>>> @@ -588,6 +590,8 @@ MiscRegFile::updateCPU()
> >>>>>
> >>>>> //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol
> regs
> >>>>> if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) ==
> 0) {
> >>>>> + cout << "TCHALT: " << bits(tc_halt, TCH_H)
> >>>>> + << "TCStatus:" << bits(tc_status, TCS_A) << endl;
> >>>>> haltThread(cpu->getContext(tid));
> >>>>> } else if (bits(tc_halt, TCH_H) == 0 && bits(tc_status,
> TCS_A) == 1)
> >>>>> {
> >>>>> restoreThread(cpu->getContext(tid));
> >>>>> diff -r 6f9923f77ced -r b2b20a241e92 src/cpu/exetrace.cc
> >>>>> --- a/src/cpu/exetrace.cc Tue Nov 18 16:03:31 2008 -0500
> >>>>> +++ b/src/cpu/exetrace.cc Fri Nov 21 21:28:36 2008 -0500
> >>>>> @@ -50,8 +50,21 @@ Trace::ExeTracerRecord::dump()
> >>>>> {
> >>>>> ostream &outs = Trace::output();
> >>>>>
> >>>>> - if (IsOn(ExecTicks))
> >>>>> - ccprintf(outs, "%7d: ", when);
> >>>>> + if (IsOn(ExecTicks))
> >>>>> + // {
> >>>>> + //if (!stageTrace) {
> >>>>> + ccprintf(outs, "%7d: ", when);
> >>>>> + /*} else {
> >>>>> + //outs << dec << "\t";
> >>>>> + ccprintf(outs, "");
> >>>>> + for (int i=0; i < stageCycle.size(); i++) {
> >>>>> + if (i < stageCycle.size() - 1)
> >>>>> + outs << dec << stageCycle[i] << "-";
> >>>>> + else
> >>>>> + outs << dec << stageCycle[i] << ":";
> >>>>> + }
> >>>>> + }
> >>>>> + }*/
> >>>>>
> >>>>> outs << thread->getCpuPtr()->name() << " ";
> >>>>>
> >>>>> diff -r 6f9923f77ced -r b2b20a241e92 src/cpu/mixie/MixieCPU.py
> >>>>> --- a/src/cpu/mixie/MixieCPU.py Tue Nov 18 16:03:31 2008 -0500
> >>>>> +++ b/src/cpu/mixie/MixieCPU.py Fri Nov 21 21:28:36 2008 -0500
> >>>>> @@ -41,7 +41,8 @@ class MixieCPU(BaseCPU):
> >>>>> class MixieCPU(BaseCPU):
> >>>>> type = 'MixieCPU'
> >>>>> activity = Param.Unsigned(0, "Initial count")
> >>>>> - numThreads = Param.Unsigned(1, "number of HW thread contexts")
> >>>>> +
> >>>>> + #numThreads = Param.Unsigned(1, "number of HW thread contexts")
> >>>>>
> >>>>> cachePorts = Param.Unsigned("Cache Ports")
> >>>>> stageWidth = Param.Unsigned(1, "Stage width")
> >>>>> diff -r 6f9923f77ced -r b2b20a241e92 src/cpu/mixie/cpu.cc
> >>>>> --- a/src/cpu/mixie/cpu.cc Tue Nov 18 16:03:31 2008 -0500
> >>>>> +++ b/src/cpu/mixie/cpu.cc Fri Nov 21 21:28:36 2008 -0500
> >>>>> @@ -283,8 +283,12 @@ MixieCPU::MixieCPU(Params *params)
> >>>>> dummyReq = new ResourceRequest(NULL, NULL, 0, 0, 0, 0);
> >>>>>
> >>>>> // Reset CPU to reset state.
> >>>>> +#if FULL_SYSTEM
> >>>>> Fault resetFault = new ResetFault();
> >>>>> resetFault->invoke(tcBase());
> >>>>> +#else
> >>>>> + reset();
> >>>>> +#endif
> >>>>>
> >>>>> // Schedule First Tick Event, CPU will reschedule itself from
> here on
> >>>>> out.
> >>>>> scheduleTickEvent(0);
> >>>>> @@ -460,7 +464,7 @@ void
> >>>>> void
> >>>>> MixieCPU::reset()
> >>>>> {
> >>>>> - miscRegFile.reset(coreType, numThreads, numVirtProcs, this);
> >>>>> + miscRegFile.reset(coreType, numThreads, numVirtProcs,
> >>>>> dynamic_cast<BaseCPU*>(this));
> >>>>> }
> >>>>>
> >>>>> Port*
> >>>>> _______________________________________________
> >>>>> m5-dev mailing list
> >>>>> m5-dev@m5sim.org
> >>>>> http://m5sim.org/mailman/listinfo/m5-dev
> >>>>>
> >>>>>
> >>>>
> >>>>
> >>>> _______________________________________________
> >>>> m5-dev mailing list
> >>>> m5-dev@m5sim.org
> >>>> http://m5sim.org/mailman/listinfo/m5-dev
> >>>>
> >>>>
> >>>
> >>>
> >>>
> >>>
> >>
> >> _______________________________________________
> >> m5-dev mailing list
> >> m5-dev@m5sim.org
> >> http://m5sim.org/mailman/listinfo/m5-dev
> >>
> >>
> > _______________________________________________
> > m5-dev mailing list
> > m5-dev@m5sim.org
> > http://m5sim.org/mailman/listinfo/m5-dev
> >
>
>
>
> --
> ----------
> Korey L Sewell
> Graduate Student - PhD Candidate
> Computer Science & Engineering
> University of Michigan
> _______________________________________________
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/m5-dev
>
>
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