Yea, I did it in a CMP, however it was more than a couple of months: 5500:57e76b2fde15, July 01, 2008.
I think Clint was working on an O3 draining and switch-out problem, however that hasn't made it into the repository yet. Nothing jumps out in the change log as a possibility since then: 10:04:00 [saidi:zeep ~/work/m5.dev] hg log -l 300 | grep -i O3 summary: O3CPU: Make the instcount debugging stuff per-cpu. summary: s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in summary: Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete. summary: O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes summary: O3: Generaize the O3 IMPL class so it isn't split out by ISA. summary: O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA. summary: O3: Generalize the O3 CPU object so it isn't split out by ISA. summary: O3CPU: Fix thread writeback logic. summary: O3CPU: Add a hack to ensure that nextPC is set correctly after syscalls. Ali On Dec 12, 2008, at 8:54 PM, Lisa Hsu wrote: > in a CMP? that's the only scenario where there's a problem, i > neglected to mention. > > > On Fri, Dec 12, 2008 at 7:23 PM, Ali Saidi <[email protected]> wrote: > I haven't done it with the head. I've been using code that is a couple > of months old. Changes between now and then would be a good place to > look. > > Ali > > > > On Dec 12, 2008, at 3:59 PM, Lisa Hsu wrote: > > > The former case is still broken (were were ever supposed to be able > > to restore directly to O3? i can't remember). > > > > The latter was my fault, i added a new cache option that was not > > caught by all the "if not options.caches" statements in > Simulation.py. > > > > But the bad news is Bob Nagel's complaint appears to be legit, I'm > > getting the same CountedDrain error he is. > > > > Lisa > > > > On Fri, Dec 12, 2008 at 3:35 PM, Lisa Hsu <[email protected]> > wrote: > > Anyone do this lately? It appears to be broken. Whether restoring > > directly into O3 or using the --standard-switch, both die. In the > > former case it's because there are no activeThreads, and in the 2nd > > because it appears the O3 cpu is getting recvAtomic callbacks before > > the switchover has even occurred. It seems strange that something > > so fundamental could be hiding away as broken. > > > > Lisa > > > > > > > > _______________________________________________ > > m5-dev mailing list > > [email protected] > > http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
