changeset e3a6f53818fe in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e3a6f53818fe
description:
X86: Move the function that prints memory args into the inst base class.
diffstat:
2 files changed, 20 insertions(+)
src/arch/x86/insts/static_inst.cc | 19 +++++++++++++++++++
src/arch/x86/insts/static_inst.hh | 1 +
diffs (107 lines):
diff -r 07f635cab026 -r e3a6f53818fe src/arch/x86/insts/microldstop.cc
--- a/src/arch/x86/insts/microldstop.cc Tue Jan 06 22:44:59 2009 -0800
+++ b/src/arch/x86/insts/microldstop.cc Tue Jan 06 22:46:28 2009 -0800
@@ -64,7 +64,6 @@
const SymbolTable *symtab) const
{
std::stringstream response;
- bool someAddr = false;
printMnemonic(response, instMnem, mnemonic);
if(flags[IsLoad])
@@ -72,32 +71,8 @@
else
printSrcReg(response, 2, dataSize);
response << ", ";
- printSegment(response, segment);
- response << ":[";
- if(scale != 0 && _srcRegIdx[0] != ZeroReg)
- {
- if(scale != 1)
- ccprintf(response, "%d*", scale);
- printSrcReg(response, 0, addressSize);
- someAddr = true;
- }
- if(_srcRegIdx[1] != ZeroReg)
- {
- if(someAddr)
- response << " + ";
- printSrcReg(response, 1, addressSize);
- someAddr = true;
- }
- if(disp != 0)
- {
- if(someAddr)
- response << " + ";
- ccprintf(response, "%#x", disp);
- someAddr = true;
- }
- if(!someAddr)
- response << "0";
- response << "]";
+ printMem(response, segment, scale, index, base, disp,
+ addressSize, false);
return response.str();
}
}
diff -r 07f635cab026 -r e3a6f53818fe src/arch/x86/insts/static_inst.cc
--- a/src/arch/x86/insts/static_inst.cc Tue Jan 06 22:44:59 2009 -0800
+++ b/src/arch/x86/insts/static_inst.cc Tue Jan 06 22:46:28 2009 -0800
@@ -240,6 +240,44 @@
}
}
+ void X86StaticInst::printMem(std::ostream &os, uint8_t segment,
+ uint8_t scale, RegIndex index, RegIndex base,
+ uint64_t disp, uint8_t addressSize, bool rip) const
+ {
+ bool someAddr = false;
+ printSegment(os, segment);
+ os << ":[";
+ if (rip) {
+ os << "rip";
+ someAddr = true;
+ } else {
+ if (scale != 0 && index != ZeroReg)
+ {
+ if(scale != 1)
+ ccprintf(os, "%d*", scale);
+ printReg(os, index, addressSize);
+ someAddr = true;
+ }
+ if (base != ZeroReg)
+ {
+ if(someAddr)
+ os << " + ";
+ printReg(os, base, addressSize);
+ someAddr = true;
+ }
+ }
+ if (disp != 0)
+ {
+ if(someAddr)
+ os << " + ";
+ ccprintf(os, "%#x", disp);
+ someAddr = true;
+ }
+ if (!someAddr)
+ os << "0";
+ os << "]";
+ }
+
std::string X86StaticInst::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
diff -r 07f635cab026 -r e3a6f53818fe src/arch/x86/insts/static_inst.hh
--- a/src/arch/x86/insts/static_inst.hh Tue Jan 06 22:44:59 2009 -0800
+++ b/src/arch/x86/insts/static_inst.hh Tue Jan 06 22:46:28 2009 -0800
@@ -89,6 +89,9 @@
void printReg(std::ostream &os, int reg, int size) const;
void printSrcReg(std::ostream &os, int reg, int size) const;
void printDestReg(std::ostream &os, int reg, int size) const;
+ void printMem(std::ostream &os, uint8_t segment,
+ uint8_t scale, RegIndex index, RegIndex base,
+ uint64_t disp, uint8_t addressSize, bool rip) const;
inline uint64_t merge(uint64_t into, uint64_t val, int size) const
{
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
