I've been putting off starting a discussion about this since I know some people are otherwise occupied, but it would be useful for it to at least be in the back of someones mind. I haven't spent a huge amount of time thinking about this recently, but I see two possible ways to handle it.
1. Translation is reworked so that it can be delayed like memory transations. In atomic mode it could be blocking and immediate, and in timing mode the CPU would get a call back. This isn't ideal because it would require changes to the CPU models which would potentially cause performance overhead for the other ISAs, potentially break ARM (more?), and would be painful to add to O3 in the long term. It's the most realistic, though, in terms of mimicking actual CPUs. 2. Make the TLB miss fault invoke whichever other faults may come up inside it's own invoke method. This would be comparatively easy, but would be inaccurate as far as performance. It also goes behind the CPU's back as far as who is in control of faults/exceptions, etc., and could cause problems with generic statistics for instance. I don't know if such statistics exist. Gabe _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
