> So does this mean that the TLB is on the other side of a port but still > part of the CPU? That would be one way to ensure there's no intervening > cache. Is there any way to pass faults around over a port? Or would this > be more of a port-like connection to decouple request/response but to > fit into the CPU more snugly? It would be nice to reuse ports rather > than inventing some new system, but if they don't solve the problem > without distorting them too much (for reasonable values of too much) > then I guess that's that.
My only hesitation with making the TLB us a port interface is that this would slow down the hit path. Slowing down the hit path has always been something we've tried to avoid. Nate _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
