changeset baf5d5c96c68 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=baf5d5c96c68
description:
        pseudo inst: Add new wake cpu instruction for sending a message to wake 
a cpu.
        It's instantaneous and so it's somewhat bogus, but it's a first step.

diffstat:

6 files changed, 17 insertions(+)
src/arch/alpha/isa/decoder.isa |    3 +++
src/sim/pseudo_inst.cc         |    9 +++++++++
src/sim/pseudo_inst.hh         |    1 +
util/m5/m5op.h                 |    1 +
util/m5/m5op_alpha.S           |    2 ++
util/m5/m5ops.h                |    1 +

diffs (84 lines):

diff -r 57f9f8b8e62f -r baf5d5c96c68 src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa    Sat Jan 24 07:27:21 2009 -0800
+++ b/src/arch/alpha/isa/decoder.isa    Sat Jan 24 07:27:22 2009 -0800
@@ -815,6 +815,9 @@
             0x07: rpns({{
                 R0 = PseudoInst::rpns(xc->tcBase());
             }}, IsNonSpeculative, IsUnverifiable);
+            0x09: wakeCPU({{
+                PseudoInst::wakeCPU(xc->tcBase(), R16);
+            }}, IsNonSpeculative, IsUnverifiable);
             0x10: deprecated_ivlb({{
                 warn_once("Obsolete M5 ivlb instruction encountered.\n");
             }});
diff -r 57f9f8b8e62f -r baf5d5c96c68 src/sim/pseudo_inst.cc
--- a/src/sim/pseudo_inst.cc    Sat Jan 24 07:27:21 2009 -0800
+++ b/src/sim/pseudo_inst.cc    Sat Jan 24 07:27:22 2009 -0800
@@ -138,6 +138,15 @@
 }
 
 void
+wakeCPU(ThreadContext *tc, uint64_t cpuid)
+{
+    System *sys = tc->getSystemPtr();
+    ThreadContext *other_tc = sys->threadContexts[cpuid];
+    if (other_tc->status() == ThreadContext::Suspended)
+        other_tc->activate();
+}
+
+void
 m5exit(ThreadContext *tc, Tick delay)
 {
     Tick when = curTick + delay * Clock::Int::ns;
diff -r 57f9f8b8e62f -r baf5d5c96c68 src/sim/pseudo_inst.hh
--- a/src/sim/pseudo_inst.hh    Sat Jan 24 07:27:21 2009 -0800
+++ b/src/sim/pseudo_inst.hh    Sat Jan 24 07:27:22 2009 -0800
@@ -55,6 +55,7 @@
 #endif
 
 uint64_t rpns(ThreadContext *tc);
+void wakeCPU(ThreadContext *tc, uint64_t cpuid);
 void m5exit(ThreadContext *tc, Tick delay);
 void resetstats(ThreadContext *tc, Tick delay, Tick period);
 void dumpstats(ThreadContext *tc, Tick delay, Tick period);
diff -r 57f9f8b8e62f -r baf5d5c96c68 util/m5/m5op.h
--- a/util/m5/m5op.h    Sat Jan 24 07:27:21 2009 -0800
+++ b/util/m5/m5op.h    Sat Jan 24 07:27:22 2009 -0800
@@ -40,6 +40,7 @@
 void quiesceCycle(uint64_t cycles);
 uint64_t quiesceTime(void);
 uint64_t rpns();
+void wakeCPU(uint64_t cpuid);
 
 void m5_exit(uint64_t ns_delay);
 uint64_t m5_initparam(void);
diff -r 57f9f8b8e62f -r baf5d5c96c68 util/m5/m5op_alpha.S
--- a/util/m5/m5op_alpha.S      Sat Jan 24 07:27:21 2009 -0800
+++ b/util/m5/m5op_alpha.S      Sat Jan 24 07:27:22 2009 -0800
@@ -60,6 +60,7 @@
 #define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func)
 #define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
 #define RPNS INST(m5_op, 0, 0, rpns_func)
+#define WAKE_CPU(r1) INST(m5_op, r1, 0, wakecpu_func)
 #define M5EXIT(reg) INST(m5_op, reg, 0, exit_func)
 #define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func)
 #define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func)
@@ -81,6 +82,7 @@
 SIMPLE_OP(quiesceCycle, QUIESCECYC(16))
 SIMPLE_OP(quiesceTime, QUIESCETIME)
 SIMPLE_OP(rpns, RPNS)
+SIMPLE_OP(wakeCPU, WAKE_CPU(16))
 SIMPLE_OP(m5_exit, M5EXIT(16))
 SIMPLE_OP(m5_initparam, INITPARAM(0))
 SIMPLE_OP(m5_loadsymbol, LOADSYMBOL(0))
diff -r 57f9f8b8e62f -r baf5d5c96c68 util/m5/m5ops.h
--- a/util/m5/m5ops.h   Sat Jan 24 07:27:21 2009 -0800
+++ b/util/m5/m5ops.h   Sat Jan 24 07:27:22 2009 -0800
@@ -35,6 +35,7 @@
 #define quiescecycle_func       0x03
 #define quiescetime_func        0x04
 #define rpns_func               0x07
+#define wakecpu_func            0x09
 #define deprecated1_func        0x10 // obsolete ivlb
 #define deprecated2_func        0x11 // obsolete ivle
 #define deprecated3_func        0x20 // deprecated exit function
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