changeset d12ff89c7692 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d12ff89c7692
description:
X86: Fix a bug in the iret microcode.
diffstat:
1 file changed, 2 insertions(+), 1 deletion(-)
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
| 3 ++-
diffs (20 lines):
diff -r 219a39f70082 -r d12ff89c7692
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Sun Jan 25 20:30:51 2009 -0800
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Sun Jan 25 20:31:17 2009 -0800
@@ -75,6 +75,8 @@
ld t2, ss, [1, t0, rsp], "1 * env.stackSize", dataSize=ssz
ld t3, ss, [1, t0, rsp], "2 * env.stackSize", dataSize=ssz
+ # Read the handy m5 register for use later
+ rdm5reg t4
###
@@ -89,7 +91,6 @@
br label("protToVirtFallThrough"), flags=(nCECF,)
#CPL=0
- rdm5reg t4
andi t0, t4, 0x30, flags=(EZF,)
br label("protToVirtFallThrough"), flags=(nCEZF,)
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