changeset 4cc05b7f2a97 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4cc05b7f2a97
description:
X86: Fix some incorrect register widths.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
src/arch/x86/isa/operands.isa | 4 ++--
diffs (13 lines):
diff -r 47ada83a8958 -r 4cc05b7f2a97 src/arch/x86/isa/operands.isa
--- a/src/arch/x86/isa/operands.isa Sun Feb 01 00:15:38 2009 -0800
+++ b/src/arch/x86/isa/operands.isa Sun Feb 01 00:18:13 2009 -0800
@@ -159,7 +159,7 @@
'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
'MiscRegDest': ('ControlReg', 'uqw', 'dest', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
'MiscRegSrc1': ('ControlReg', 'uqw', 'src1', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
- 'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None,
['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
- 'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None,
None), 212),
+ 'TscOp': ('ControlReg', 'uqw', 'MISCREG_TSC', (None, None,
['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
+ 'M5Reg': ('ControlReg', 'uqw', 'MISCREG_M5_REG', (None, None,
None), 212),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad',
'IsStore'), 300)
}};
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