changeset 1349786dd9a7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1349786dd9a7
description:
X86: Hook up the IDE controller interrupt line.
diffstat:
2 files changed, 3 insertions(+), 2 deletions(-)
src/dev/x86/SouthBridge.py | 1 +
src/dev/x86/pc.cc | 4 ++--
diffs (30 lines):
diff -r 08c65e29e57e -r 1349786dd9a7 src/dev/x86/SouthBridge.py
--- a/src/dev/x86/SouthBridge.py Sun Feb 01 00:24:26 2009 -0800
+++ b/src/dev/x86/SouthBridge.py Sun Feb 01 00:25:15 2009 -0800
@@ -87,6 +87,7 @@
ide.BAR3LegacyIO = True
ide.BAR4 = 1
ide.Command = 1
+ ide.InterruptLine = 20
def attachIO(self, bus):
# Route interupt signals
diff -r 08c65e29e57e -r 1349786dd9a7 src/dev/x86/pc.cc
--- a/src/dev/x86/pc.cc Sun Feb 01 00:24:26 2009 -0800
+++ b/src/dev/x86/pc.cc Sun Feb 01 00:25:15 2009 -0800
@@ -127,13 +127,13 @@
void
Pc::postPciInt(int line)
{
- panic("Need implementation\n");
+ southBridge->ioApic->signalInterrupt(line);
}
void
Pc::clearPciInt(int line)
{
- panic("Need implementation\n");
+ warn_once("Tried to clear PCI interrupt %d\n", line);
}
Addr
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
