Ok. Sometimes there isn't a very good single piece of documentation for this stuff and I have to extrapolate from miscellaneous specs, random websites and guesses. In the cases where there is an good source of information I'll add a reference.
Gabe nathan binkert wrote: > I know that I wasn't good about this with Alpha, but a comment in the > code with a reference to documentation that explains the numbers > you've stuck in there would generally be very nice. > > > Nate > > On Sun, Feb 1, 2009 at 5:18 PM, Gabe Black <[email protected]> wrote: > >> changeset a2c317cefcf8 in /z/repo/m5 >> details: http://repo.m5sim.org/m5?cmd=changeset;node=a2c317cefcf8 >> description: >> X86: Configure the first PCI interrupt. >> >> diffstat: >> >> 3 files changed, 39 insertions(+), 1 deletion(-) >> configs/common/FSConfig.py | 31 +++++++++++++++++++++++++++++++ >> src/dev/x86/SouthBridge.py | 3 ++- >> src/dev/x86/pc.cc | 6 ++++++ >> >> diffs (77 lines): >> >> diff -r 1349786dd9a7 -r a2c317cefcf8 configs/common/FSConfig.py >> --- a/configs/common/FSConfig.py Sun Feb 01 00:25:15 2009 -0800 >> +++ b/configs/common/FSConfig.py Sun Feb 01 00:26:10 2009 -0800 >> @@ -212,6 +212,19 @@ >> self.intel_mp_table.add_entry(io_apic) >> isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') >> self.intel_mp_table.add_entry(isa_bus) >> + pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') >> + self.intel_mp_table.add_entry(pci_bus) >> + connect_busses = X86IntelMPBusHierarchy(bus_id=0, >> + subtractive_decode=True, parent_bus=1) >> + self.intel_mp_table.add_entry(connect_busses) >> + pci_dev4_inta = X86IntelMPIOIntAssignment( >> + interrupt_type = 'INT', >> + polarity = 'ConformPolarity', >> + trigger = 'ConformTrigger', >> + source_bus_id = 1, >> + source_bus_irq = 0 + (4 << 2), >> + dest_io_apic_id = 1, >> + dest_io_apic_intin = 16) >> assign_8259_0_to_apic = X86IntelMPIOIntAssignment( >> interrupt_type = 'ExtInt', >> polarity = 'ConformPolarity', >> @@ -266,6 +279,24 @@ >> dest_io_apic_id = 1, >> dest_io_apic_intin = 12) >> self.intel_mp_table.add_entry(assign_12_to_apic) >> + assign_8259_14_to_apic = X86IntelMPIOIntAssignment( >> + interrupt_type = 'ExtInt', >> + polarity = 'ConformPolarity', >> + trigger = 'ConformTrigger', >> + source_bus_id = 0, >> + source_bus_irq = 14, >> + dest_io_apic_id = 1, >> + dest_io_apic_intin = 0) >> + self.intel_mp_table.add_entry(assign_8259_14_to_apic) >> + assign_14_to_apic = X86IntelMPIOIntAssignment( >> + interrupt_type = 'INT', >> + polarity = 'ConformPolarity', >> + trigger = 'ConformTrigger', >> + source_bus_id = 0, >> + source_bus_irq = 14, >> + dest_io_apic_id = 1, >> + dest_io_apic_intin = 14) >> + self.intel_mp_table.add_entry(assign_14_to_apic) >> >> >> def makeLinuxX86System(mem_mode, mdesc = None): >> diff -r 1349786dd9a7 -r a2c317cefcf8 src/dev/x86/SouthBridge.py >> --- a/src/dev/x86/SouthBridge.py Sun Feb 01 00:25:15 2009 -0800 >> +++ b/src/dev/x86/SouthBridge.py Sun Feb 01 00:26:10 2009 -0800 >> @@ -87,7 +87,8 @@ >> ide.BAR3LegacyIO = True >> ide.BAR4 = 1 >> ide.Command = 1 >> - ide.InterruptLine = 20 >> + ide.InterruptLine = 14 >> + ide.InterruptPin = 1 >> >> def attachIO(self, bus): >> # Route interupt signals >> diff -r 1349786dd9a7 -r a2c317cefcf8 src/dev/x86/pc.cc >> --- a/src/dev/x86/pc.cc Sun Feb 01 00:25:15 2009 -0800 >> +++ b/src/dev/x86/pc.cc Sun Feb 01 00:26:10 2009 -0800 >> @@ -101,6 +101,12 @@ >> entry.vector = 0x2C; >> ioApic.writeReg(0x28, entry.bottomDW); >> ioApic.writeReg(0x29, entry.topDW); >> + entry.vector = 0x2E; >> + ioApic.writeReg(0x2C, entry.bottomDW); >> + ioApic.writeReg(0x2D, entry.topDW); >> + entry.vector = 0x30; >> + ioApic.writeReg(0x30, entry.bottomDW); >> + ioApic.writeReg(0x31, entry.topDW); >> } >> >> Tick >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> >> >> > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
