changeset cd969187e2d3 in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=cd969187e2d3
description:
Fix some copyrights
diffstat:
1 file changed, 566 insertions(+), 646 deletions(-)
import_mixie | 1212 +++++++++++++++++++++++++++-------------------------------
diffs (truncated from 1772 to 300 lines):
diff -r 0b6421ada742 -r cd969187e2d3 import_mixie
--- a/import_mixie Wed Feb 04 14:00:21 2009 -0800
+++ b/import_mixie Wed Feb 04 16:31:44 2009 -0800
@@ -1,63 +1,7 @@
-diff -r db1653549204 src/arch/mips/locked_mem.hh
---- a/src/arch/mips/locked_mem.hh Thu Nov 20 19:08:46 2008 -0800
-+++ b/src/arch/mips/locked_mem.hh Mon Nov 24 18:03:46 2008 -0500
-@@ -1,31 +1,31 @@
- /*
-- * Copyright (c) 2006-2007 The Regents of The University of Michigan
-- * All rights reserved.
-+ * Copyright (c) 2006, 2007
-+ * The Regents of The University of Michigan
-+ * All Rights Reserved
- *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are
-- * met: redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer;
-- * redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution;
-- * neither the name of the copyright holders nor the names of its
-- * contributors may be used to endorse or promote products derived from
-- * this software without specific prior written permission.
-+ * This code is part of the M5 simulator.
- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ * Permission is granted to use, copy, create derivative works and
-+ * redistribute this software and such derivative works for any
-+ * purpose, so long as the copyright notice above, this grant of
-+ * permission, and the disclaimer below appear in all copies made; and
-+ * so long as the name of The University of Michigan is not used in
-+ * any advertising or publicity pertaining to the use or distribution
-+ * of this software without specific, written prior authorization.
- *
-- * Authors: Steve Reinhardt
-+ * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
-+ * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
-+ * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
-+ * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
-+ * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
-+ * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
-+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
-+ * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGES.
-+ *
-+ * Authors: Steven K. Reinhardt
- */
-
- #ifndef __ARCH_MIPS_LOCKED_MEM_HH__
-@@ -49,10 +49,11 @@ inline void
+diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
+--- a/src/arch/mips/locked_mem.hh
++++ b/src/arch/mips/locked_mem.hh
+@@ -49,10 +49,11 @@
inline void
handleLockedRead(XC *xc, Request *req)
{
@@ -72,7 +16,7 @@
}
-@@ -60,20 +61,22 @@ inline bool
+@@ -60,20 +61,22 @@
inline bool
handleLockedWrite(XC *xc, Request *req)
{
@@ -98,7 +42,7 @@
// the rest of this code is not architectural;
// it's just a debugging aid to help detect
-@@ -82,22 +85,22 @@ handleLockedWrite(XC *xc, Request *req)
+@@ -82,22 +85,22 @@
int stCondFailures = xc->readStCondFailures();
stCondFailures++;
xc->setStCondFailures(stCondFailures);
@@ -127,10 +71,10 @@
}
// store conditional failed already, so don't issue it to mem
return false;
-diff -r db1653549204 src/cpu/SConscript
---- a/src/cpu/SConscript Thu Nov 20 19:08:46 2008 -0800
-+++ b/src/cpu/SConscript Mon Nov 24 18:03:46 2008 -0500
-@@ -54,6 +54,8 @@ virtual Fault completeAcc(Packet *pkt, %
+diff --git a/src/cpu/SConscript b/src/cpu/SConscript
+--- a/src/cpu/SConscript
++++ b/src/cpu/SConscript
+@@ -54,6 +54,8 @@
virtual Fault completeAcc(Packet *pkt, %s *xc,
Trace::InstRecord *traceData) const
{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
@@ -139,7 +83,7 @@
'''
mem_ini_sig_template = '''
-@@ -82,7 +84,10 @@ def gen_cpu_exec_signatures(target, sour
+@@ -82,7 +84,10 @@
'''
for cpu in temp_cpu_list:
xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
@@ -151,19 +95,20 @@
print >> f, '''
#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
'''
-diff -r db1653549204 src/cpu/cpu_models.py
---- a/src/cpu/cpu_models.py Thu Nov 20 19:08:46 2008 -0800
-+++ b/src/cpu/cpu_models.py Mon Nov 24 18:03:46 2008 -0500
-@@ -82,3 +82,6 @@ CpuModel('O3CPU', 'o3_cpu_exec.cc',
+diff --git a/src/cpu/cpu_models.py b/src/cpu/cpu_models.py
+--- a/src/cpu/cpu_models.py
++++ b/src/cpu/cpu_models.py
+@@ -82,3 +82,6 @@
CpuModel('O3CPU', 'o3_cpu_exec.cc',
'#include "cpu/o3/isa_specific.hh"',
{ 'CPU_exec_context': 'O3DynInst' })
+CpuModel('MixieCPU', 'mixie_cpu_exec.cc',
+ '#include "cpu/mixie/mixie_dyn_inst.hh"',
+ { 'CPU_exec_context': 'MixieDynInst' })
-diff -r db1653549204 src/cpu/mixie/MixieCPU.py
---- /dev/null Thu Jan 01 00:00:00 1970 +0000
-+++ b/src/cpu/mixie/MixieCPU.py Mon Nov 24 18:03:46 2008 -0500
+diff --git a/src/cpu/mixie/MixieCPU.py b/src/cpu/mixie/MixieCPU.py
+new file mode 100644
+--- /dev/null
++++ b/src/cpu/mixie/MixieCPU.py
@@ -0,0 +1,51 @@
+from m5.params import *
+from m5.proxy import *
@@ -216,10 +161,39 @@
+ div24RepeatRate = Param.Unsigned(1, "Repeat Rate for 24-bit Divide
Operations")
+ div32Latency = Param.Unsigned(1, "Latency for 32-bit Divide Operations")
+ div32RepeatRate = Param.Unsigned(1, "Repeat Rate for 32-bit Divide
Operations")
-diff -r db1653549204 src/cpu/mixie/MixieTrace.py
---- /dev/null Thu Jan 01 00:00:00 1970 +0000
-+++ b/src/cpu/mixie/MixieTrace.py Mon Nov 24 18:03:46 2008 -0500
-@@ -0,0 +1,7 @@
+diff --git a/src/cpu/mixie/MixieTrace.py b/src/cpu/mixie/MixieTrace.py
+new file mode 100644
+--- /dev/null
++++ b/src/cpu/mixie/MixieTrace.py
+@@ -0,0 +1,35 @@
++# Copyright (c) 2007 The Regents of The University of Michigan
++# All rights reserved.
++#
++# Redistribution and use in source and binary forms, with or without
++# modification, are permitted provided that the following conditions are
++# met: redistributions of source code must retain the above copyright
++# notice, this list of conditions and the following disclaimer;
++# redistributions in binary form must reproduce the above copyright
++# notice, this list of conditions and the following disclaimer in the
++# documentation and/or other materials provided with the distribution;
++# neither the name of the copyright holders nor the names of its
++# contributors may be used to endorse or promote products derived from
++# this software without specific prior written permission.
++#
++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++#
++# Authors: Gabe Black
++
+from m5.SimObject import SimObject
+from m5.params import *
+from InstTracer import InstTracer
@@ -227,39 +201,40 @@
+class MixieTrace(InstTracer):
+ type = 'MixieTrace'
+ cxx_class = 'Trace::MixieTrace'
-diff -r db1653549204 src/cpu/mixie/SConscript
---- /dev/null Thu Jan 01 00:00:00 1970 +0000
-+++ b/src/cpu/mixie/SConscript Mon Nov 24 18:03:46 2008 -0500
+diff --git a/src/cpu/mixie/SConscript b/src/cpu/mixie/SConscript
+new file mode 100644
+--- /dev/null
++++ b/src/cpu/mixie/SConscript
@@ -0,0 +1,81 @@
+# -*- mode:python -*-
+
-+# Copyright (c) 2006
-+# The Regents of The University of Michigan
-+# All Rights Reserved
++# Copyright (c) 2006 The Regents of The University of Michigan
++# All rights reserved.
+#
-+# This code is part of the M5 simulator.
++# Redistribution and use in source and binary forms, with or without
++# modification, are permitted provided that the following conditions are
++# met: redistributions of source code must retain the above copyright
++# notice, this list of conditions and the following disclaimer;
++# redistributions in binary form must reproduce the above copyright
++# notice, this list of conditions and the following disclaimer in the
++# documentation and/or other materials provided with the distribution;
++# neither the name of the copyright holders nor the names of its
++# contributors may be used to endorse or promote products derived from
++# this software without specific prior written permission.
+#
-+# Permission is granted to use, copy, create derivative works and
-+# redistribute this software and such derivative works for any
-+# purpose, so long as the copyright notice above, this grant of
-+# permission, and the disclaimer below appear in all copies made; and
-+# so long as the name of The University of Michigan is not used in any
-+# advertising or publicity pertaining to the use or distribution of
-+# this software without specific, written prior authorization.
++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
-+# THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
-+# UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
-+# WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
-+# EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
-+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+# PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
-+# LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
-+# INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
-+# ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
-+# IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
-+# DAMAGES.
-+#
-+# Authors: Nathan L. Binkert
++# Authors: Nathan Binkert
+
+import sys
+
@@ -312,47 +287,49 @@
+ Source('thread_context.cc')
+ Source('cpu.cc')
+
-diff -r db1653549204 src/cpu/mixie/SConsopts
---- /dev/null Thu Jan 01 00:00:00 1970 +0000
-+++ b/src/cpu/mixie/SConsopts Mon Nov 24 18:03:46 2008 -0500
+diff --git a/src/cpu/mixie/SConsopts b/src/cpu/mixie/SConsopts
+new file mode 100644
+--- /dev/null
++++ b/src/cpu/mixie/SConsopts
@@ -0,0 +1,34 @@
+# -*- mode:python -*-
+
-+# Copyright (c) 2006
-+# The Regents of The University of Michigan
-+# All Rights Reserved
++# Copyright (c) 2006 The Regents of The University of Michigan
++# All rights reserved.
+#
-+# This code is part of the M5 simulator.
++# Redistribution and use in source and binary forms, with or without
++# modification, are permitted provided that the following conditions are
++# met: redistributions of source code must retain the above copyright
++# notice, this list of conditions and the following disclaimer;
++# redistributions in binary form must reproduce the above copyright
++# notice, this list of conditions and the following disclaimer in the
++# documentation and/or other materials provided with the distribution;
++# neither the name of the copyright holders nor the names of its
++# contributors may be used to endorse or promote products derived from
++# this software without specific prior written permission.
+#
-+# Permission is granted to use, copy, create derivative works and
-+# redistribute this software and such derivative works for any
-+# purpose, so long as the copyright notice above, this grant of
-+# permission, and the disclaimer below appear in all copies made; and
-+# so long as the name of The University of Michigan is not used in any
-+# advertising or publicity pertaining to the use or distribution of
-+# this software without specific, written prior authorization.
++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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