changeset d8514fbac071 in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=d8514fbac071
description:
lots of fixup
diffstat:
9 files changed, 1488 insertions(+), 1617 deletions(-)
fix_compile.diff | 94 +
fix_mdu_latency_bug | 243 +--
fix_mixie_per_stage_tracing | 186 +--
import_mixie | 2
make_mixie_cmdline_runnable | 106 -
mixie_hello_world | 2443 +++++++++++++++++++---------------------
series | 3
update_memAccFlags_return_type | 12
update_mips_ioctl_linux_call | 16
diffs (truncated from 5531 to 300 lines):
diff -r 040d328ce5de -r d8514fbac071 fix_compile.diff
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/fix_compile.diff Fri Feb 06 16:28:10 2009 -0800
@@ -0,0 +1,94 @@
+diff --git a/src/cpu/mixie/cpu.cc b/src/cpu/mixie/cpu.cc
+--- a/src/cpu/mixie/cpu.cc
++++ b/src/cpu/mixie/cpu.cc
+@@ -152,7 +152,7 @@
+ miscRegFile(this),
+ timeBuffer(2 , 2),
+ removeInstsThisCycle(false),
+- activityRec(NumStages, 10, params->activity),
++ activityRec(params->name, NumStages, 10, params->activity),
+ switchCount(0),
+ deferRegistration(false/*params->deferRegistration*/),
+ stageTracing(params->stageTracing),
+@@ -250,10 +250,10 @@
+ pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
+
+ // Take Care of 1st/Nth stages
+- if (stNum != 0)
++ if (stNum > 0)
+ pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
+- if (stNum != NumStages - 1)
+- pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
++ if (stNum < NumStages - 2)
++ pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum + 1]);
+ }
+
+ // Initialize thread specific variables
+diff --git a/src/cpu/mixie/first_stage.cc b/src/cpu/mixie/first_stage.cc
+--- a/src/cpu/mixie/first_stage.cc
++++ b/src/cpu/mixie/first_stage.cc
+@@ -144,7 +144,10 @@
+
+ #if TRACING_ON
+ inst->traceData =
+- tracer->getInstRecord(ThePipeline::NumStages,
cpu->stageTracing);
++ tracer->getInstRecord(ThePipeline::NumStages,
++ cpu->stageTracing,
++ cpu->thread[tid]->getTC());
++
+ #endif // TRACING_ON
+
+ DPRINTF(RefCount, "creation: [tid:%i]: [sn:%i]: Refcount = %i.\n",
+diff --git a/src/cpu/mixie/mixie_trace.cc b/src/cpu/mixie/mixie_trace.cc
+--- a/src/cpu/mixie/mixie_trace.cc
++++ b/src/cpu/mixie/mixie_trace.cc
+@@ -74,7 +74,8 @@
+
+ MixieTraceRecord *
+ MixieTrace::getInstRecord(Tick when, ThreadContext *tc,
+- const StaticInstPtr staticInst, Addr pc)
++ const StaticInstPtr staticInst, Addr pc,
++ const StaticInstPtr macroStaticInst, MicroPC upc)
+ {
+ return new MixieTraceRecord(ThePipeline::NumStages, true, tc);
+ }
+diff --git a/src/cpu/mixie/mixie_trace.hh b/src/cpu/mixie/mixie_trace.hh
+--- a/src/cpu/mixie/mixie_trace.hh
++++ b/src/cpu/mixie/mixie_trace.hh
+@@ -89,7 +89,8 @@
+ getInstRecord(unsigned num_stages, bool stage_tracing, ThreadContext *tc);
+
+ virtual MixieTraceRecord *getInstRecord(Tick when, ThreadContext *tc,
+- const StaticInstPtr staticInst, Addr pc);
++ const StaticInstPtr staticInst, Addr pc,
++ const StaticInstPtr macroStaticInst = NULL, MicroPC upc = 0);
+ };
+
+ /* namespace Trace */ }
+diff --git a/src/cpu/mixie/resources/cache_unit.cc
b/src/cpu/mixie/resources/cache_unit.cc
+--- a/src/cpu/mixie/resources/cache_unit.cc
++++ b/src/cpu/mixie/resources/cache_unit.cc
+@@ -450,8 +450,11 @@
+ findRequest(cache_pkt->cacheReq->getInst()));
+ assert(cache_req);
+
++#if TRACING_ON
+ // Get resource request info
+ unsigned tid = 0;
++#endif
++
+ //tid = pkt->req->getThreadNum();
+ unsigned stage_num = cache_req->getStageNum();
+ DynInstPtr inst = cache_req->inst;
+diff --git a/src/cpu/mixie/thread_context.hh b/src/cpu/mixie/thread_context.hh
+--- a/src/cpu/mixie/thread_context.hh
++++ b/src/cpu/mixie/thread_context.hh
+@@ -69,6 +69,8 @@
+
+ /** Returns a pointer to the DTB. */
+ TheISA::DTB *getDTBPtr() { return cpu->dtb; }
++
++ System *getSystemPtr() { return cpu->system; }
+
+ /** Returns a pointer to this CPU. */
+ virtual BaseCPU *getCpuPtr() { return cpu; }
diff -r 040d328ce5de -r d8514fbac071 fix_mdu_latency_bug
--- a/fix_mdu_latency_bug Wed Feb 04 16:32:10 2009 -0800
+++ b/fix_mdu_latency_bug Fri Feb 06 16:28:10 2009 -0800
@@ -1,7 +1,7 @@
-diff -r a7f780b988cc src/cpu/mixie/cpu.cc
---- a/src/cpu/mixie/cpu.cc Tue Jan 13 13:02:09 2009 -0500
-+++ b/src/cpu/mixie/cpu.cc Fri Jan 16 15:31:42 2009 -0500
-@@ -162,6 +162,7 @@ MixieCPU::MixieCPU(Params *params)
+diff --git a/src/cpu/mixie/cpu.cc b/src/cpu/mixie/cpu.cc
+--- a/src/cpu/mixie/cpu.cc
++++ b/src/cpu/mixie/cpu.cc
+@@ -162,6 +162,7 @@
cpu_params = params;
resPool = new ResourcePool(this, params);
@@ -9,150 +9,108 @@
coreType = "default"; // eventually get this from params
-diff -r a7f780b988cc src/cpu/mixie/pipeline_traits.cc
---- a/src/cpu/mixie/pipeline_traits.cc Tue Jan 13 13:02:09 2009 -0500
-+++ b/src/cpu/mixie/pipeline_traits.cc Fri Jan 16 15:31:42 2009 -0500
-@@ -105,10 +105,17 @@ bool createBackEndSchedule(DynInstPtr &i
+diff --git a/src/cpu/mixie/pipeline_traits.cc
b/src/cpu/mixie/pipeline_traits.cc
+--- a/src/cpu/mixie/pipeline_traits.cc
++++ b/src/cpu/mixie/pipeline_traits.cc
+@@ -105,9 +105,16 @@
E->needs(DCache, CacheUnit::InitiateReadData);
}
} else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
- E->needs(MDU, MultDivUnit::MultDiv);
+ E->needs(MDU, MultDivUnit::StartMultDiv);
-+
-+ // ZERO-LATENCY Multiply
-+ // E->needs(MDU, MultDivUnit::MultDiv);
++
++ // ZERO-LATENCY Multiply:
++ // E->needs(MDU, MultDivUnit::MultDiv);
} else {
E->needs(ExecUnit, ExecutionUnit::ExecuteInst);
- }
++ }
+
+ if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
-+ M->needs(MDU, MultDivUnit::EndMultDiv);
-+ }
++ M->needs(MDU, MultDivUnit::EndMultDiv);
+ }
if ( inst->isLoad() ) {
- M->needs(DCache, CacheUnit::CompleteReadData);
-diff -r a7f780b988cc src/cpu/mixie/resource.cc
---- a/src/cpu/mixie/resource.cc Tue Jan 13 13:02:09 2009 -0500
-+++ b/src/cpu/mixie/resource.cc Fri Jan 16 15:31:42 2009 -0500
-@@ -8,33 +8,48 @@ Resource::Resource(string res_name, int
- int res_latency, MixieCPU *_cpu)
+diff --git a/src/cpu/mixie/resource.cc b/src/cpu/mixie/resource.cc
+--- a/src/cpu/mixie/resource.cc
++++ b/src/cpu/mixie/resource.cc
+@@ -40,17 +40,27 @@
: resName(res_name), id(res_id),
width(res_width), latency(res_latency), cpu(_cpu)
-+{
+ {
+ // Use to deny a instruction a resource.
+ deniedReq = new ResourceRequest(this, NULL, 0, 0, 0, 0);
-+
-+}
-+
-+std::string
-+Resource::name()
-+{
-+ return cpu->name() + "." + resName;
+}
+
+void
-+Resource::regStats()
++Resource::init()
+{
-+ instReqsProcessed
-+ .name(name() + ".instReqsProcessed")
-+ .desc("Number of Instructions Requests that completed in this
resource.");
-+}
-+
-+
-+void
-+Resource::init()
- {
// Set Up Resource Events to Appropriate Resource BandWidth
resourceEvent = new ResourceEvent[width];
-+ initSlots(this);
++ initSlots();
+}
+
-+void
-+Resource::initSlots(Resource *_res)
++void
++Resource::initSlots()
+{
-+ DPRINTF(Resource, "Initializing %i slots.\n", width);
-+
// Add available slot numbers for resource
for (int slot_idx = 0; slot_idx < width; slot_idx++) {
availSlots.push_back(slot_idx);
-- resourceEvent[slot_idx].init(this, slot_idx);
-- }
+ resourceEvent[slot_idx].init(this, slot_idx);
+ }
-
- // Use to deny a instruction a resource.
- deniedReq = new ResourceRequest(this, NULL, 0, 0, 0, 0);
--}
--
--std::string
--Resource::name()
--{
-- return cpu->name() + "." + resName;
--}
--
--void
--Resource::regStats()
--{
-- instReqsProcessed
-- .name(name() + ".instReqsProcessed")
-- .desc("Number of Instructions Requests that completed in this
resource.");
--}
-+ resourceEvent[slot_idx].init(_res, slot_idx);
-+ }
-+}
-+
+ }
- int
- Resource::slotsAvail()
-@@ -67,19 +82,25 @@ Resource::freeSlot(int slot_idx)
+ std::string
+@@ -98,19 +108,25 @@
}
-+// TODO: More efficiently search for instruction's slot
-+// within resource.
++// TODO: More efficiently search for instruction's slot within
++// resource.
int
Resource::findSlot(DynInstPtr inst)
{
- /* list<DynInstPtr>::iterator list_it = instList.begin();
--
++ map<int, ResReqPtr>::iterator map_it = reqMap.begin();
++ map<int, ResReqPtr>::iterator map_end = reqMap.end();
+
- while (list_it != instList.end()) {
- if ((*list_it) == inst) {
- return (*list_i;
-- }
-- }
++ int slot_num = -1;
++
++ while (map_it != map_end) {
++ if ((*map_it).second->getInst()->seqNum ==
++ inst->seqNum) {
++ slot_num = (*map_it).second->getSlot();
+ }
++ map_it++;
+ }
- */
- panic("Shouldnt be using this function!\n");
- return -1;
-+ map<int, ResReqPtr>::iterator map_it = reqMap.begin();
-+ map<int, ResReqPtr>::iterator map_end = reqMap.end();
-+
-+ int slot_num = -1;
-+
-+ while (map_it != map_end) {
-+ if ((*map_it).second->getInst()->seqNum ==
-+ inst->seqNum) {
-+ slot_num = (*map_it).second->getSlot();
-+ }
-+ map_it++;
-+ }
+
+ return slot_num;
}
int
-@@ -288,8 +309,10 @@ void
+@@ -319,8 +335,10 @@
void
Resource::scheduleExecution(int slot_num)
{
- if (latency >= 1) {
- scheduleEvent(slot_num, latency);
+ int res_latency = getLatency(slot_num);
-+
++
+ if (res_latency >= 1) {
+ scheduleEvent(slot_num, res_latency);
} else {
execute(slot_num);
}
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
