changeset 71012a6974ed in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=71012a6974ed
description:
Add some commit messages for these patches
diffstat:
6 files changed, 38 insertions(+), 68 deletions(-)
import_mixie | 19 +++++++++++++++----
make_mixie_cmdline_runnable | 33 ++++++---------------------------
prepare_cpus.diff | 5 +++++
prepare_exetrace.diff | 4 ++++
prepare_mips.diff | 41 ++++-------------------------------------
update_mips_ioctl_linux_call | 4 ++++
diffs (207 lines):
diff -r d33c963656cb -r 71012a6974ed import_mixie
--- a/import_mixie Fri Feb 06 17:17:07 2009 -0800
+++ b/import_mixie Fri Feb 06 17:32:54 2009 -0800
@@ -1,3 +1,10 @@
+From: Korey Sewell <[email protected]>
+
+InOrder: Import new inorder CPU model from MIPS.
+This model currently only works in MIPS_SE mode, so it will take some effort
+to clean it up and make it generally useful. Hopefully people are willing to
+help make that happen!
+
diff --git a/src/cpu/cpu_models.py b/src/cpu/cpu_models.py
--- a/src/cpu/cpu_models.py
+++ b/src/cpu/cpu_models.py
@@ -373,7 +380,7 @@
new file mode 100644
--- /dev/null
+++ b/src/cpu/mixie/cpu.cc
-@@ -0,0 +1,1318 @@
+@@ -0,0 +1,1322 @@
+/*
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
@@ -661,8 +668,12 @@
+ dummyReq = new ResourceRequest(NULL, NULL, 0, 0, 0, 0);
+
+ // Reset CPU to reset state.
++#if FULL_SYSTEM
+ Fault resetFault = new ResetFault();
+ resetFault->invoke(tcBase());
++#else
++ reset();
++#endif
+
+ // Schedule First Tick Event, CPU will reschedule itself from here on out.
+ scheduleTickEvent(0);
@@ -838,7 +849,7 @@
+void
+MixieCPU::reset()
+{
-+ miscRegFile.reset(coreType, numThreads, numVirtProcs, this);
++ miscRegFile.reset(coreType, numThreads, numVirtProcs,
dynamic_cast<BaseCPU*>(this));
+}
+
+Port*
@@ -4667,7 +4678,7 @@
+namespace Trace {
+
+inline void
-+Trace::MixieTraceRecord::printTicks(std::ostream &outs)
++Trace::MixieTraceRecord::dumpTicks(std::ostream &outs)
+{
+ if (!stageTrace) {
+ ccprintf(outs, "%7d: ", when);
@@ -4781,7 +4792,7 @@
+ bool stageTrace;
+ std::vector<Tick> stageCycle;
+
-+ void printTicks(std::ostream &outs);
++ void dumpTicks(std::ostream &outs);
+
+ void
+ setStageCycle(int num_stage, Tick cur_cycle)
diff -r d33c963656cb -r 71012a6974ed make_mixie_cmdline_runnable
--- a/make_mixie_cmdline_runnable Fri Feb 06 17:17:07 2009 -0800
+++ b/make_mixie_cmdline_runnable Fri Feb 06 17:32:54 2009 -0800
@@ -1,3 +1,7 @@
+From: Korey Sewell <[email protected]>
+
+Configs: Add support for the InOrder CPU model
+
diff --git a/configs/common/Options.py b/configs/common/Options.py
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -5,7 +9,7 @@
# system options
parser.add_option("-d", "--detailed", action="store_true")
parser.add_option("-t", "--timing", action="store_true")
-+parser.add_option("--mixie", action="store_true")
++parser.add_option("--inorder", action="store_true")
parser.add_option("-n", "--num-cpus", type="int", default=1)
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
@@ -16,7 +20,7 @@
print "O3 CPU must be used with caches"
sys.exit(1)
class TmpClass(DerivO3CPU): pass
-+ elif options.mixie:
++ elif options.inorder:
+ if not options.caches:
+ print "Mixie CPU must be used with caches"
+ sys.exit(1)
@@ -24,28 +28,3 @@
else:
class TmpClass(AtomicSimpleCPU): pass
atomic = True
-diff --git a/src/cpu/mixie/cpu.cc b/src/cpu/mixie/cpu.cc
---- a/src/cpu/mixie/cpu.cc
-+++ b/src/cpu/mixie/cpu.cc
-@@ -285,8 +285,12 @@
- dummyReq = new ResourceRequest(NULL, NULL, 0, 0, 0, 0);
-
- // Reset CPU to reset state.
-+#if FULL_SYSTEM
- Fault resetFault = new ResetFault();
- resetFault->invoke(tcBase());
-+#else
-+ reset();
-+#endif
-
- // Schedule First Tick Event, CPU will reschedule itself from here on out.
- scheduleTickEvent(0);
-@@ -462,7 +466,7 @@
- void
- MixieCPU::reset()
- {
-- miscRegFile.reset(coreType, numThreads, numVirtProcs, this);
-+ miscRegFile.reset(coreType, numThreads, numVirtProcs,
dynamic_cast<BaseCPU*>(this));
- }
-
- Port*
diff -r d33c963656cb -r 71012a6974ed prepare_cpus.diff
--- a/prepare_cpus.diff Fri Feb 06 17:17:07 2009 -0800
+++ b/prepare_cpus.diff Fri Feb 06 17:32:54 2009 -0800
@@ -1,3 +1,8 @@
+From: Korey Sewell <[email protected]>
+
+CPU: Prepare CPU models for the new in-order CPU model.
+Some new functions and forward declarations are necessary to make things work
+
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
diff -r d33c963656cb -r 71012a6974ed prepare_exetrace.diff
--- a/prepare_exetrace.diff Fri Feb 06 17:17:07 2009 -0800
+++ b/prepare_exetrace.diff Fri Feb 06 17:32:54 2009 -0800
@@ -1,3 +1,7 @@
+From: Korey Sewell <[email protected]>
+
+ExeTrace: Allow subclasses of the tracer to define their own prefix to dump
+
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
diff -r d33c963656cb -r 71012a6974ed prepare_mips.diff
--- a/prepare_mips.diff Fri Feb 06 17:17:07 2009 -0800
+++ b/prepare_mips.diff Fri Feb 06 17:32:54 2009 -0800
@@ -1,3 +1,7 @@
+From: Korey Sewell <[email protected]>
+
+MIPS: Fix locked memory instructions
+
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -71,40 +75,3 @@
}
// store conditional failed already, so don't issue it to mem
return false;
-diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
---- a/src/arch/mips/mt.hh
-+++ b/src/arch/mips/mt.hh
-@@ -68,7 +68,7 @@
- }
-
- template <class TC>
--inline void
-+void
- haltThread(TC *tc)
- {
- if (tc->status() == TC::Active) {
-diff --git a/src/arch/mips/regfile/misc_regfile.cc
b/src/arch/mips/regfile/misc_regfile.cc
---- a/src/arch/mips/regfile/misc_regfile.cc
-+++ b/src/arch/mips/regfile/misc_regfile.cc
-@@ -179,8 +179,10 @@
- }
- //@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
- void
--MiscRegFile::reset(std::string core_name, unsigned num_threads,
-- unsigned num_vpes, BaseCPU *_cpu)
-+MiscRegFile::reset(std::string core_name,
-+ unsigned num_threads,
-+ unsigned num_vpes,
-+ BaseCPU *_cpu)
- {
- DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
- num_threads, num_vpes);
-@@ -588,6 +590,8 @@
-
- //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
- if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) == 0) {
-+ cout << "TCHALT: " << bits(tc_halt, TCH_H)
-+ << "TCStatus:" << bits(tc_status, TCS_A) << endl;
- haltThread(cpu->getContext(tid));
- } else if (bits(tc_halt, TCH_H) == 0 && bits(tc_status, TCS_A) == 1) {
- restoreThread(cpu->getContext(tid));
diff -r d33c963656cb -r 71012a6974ed update_mips_ioctl_linux_call
--- a/update_mips_ioctl_linux_call Fri Feb 06 17:17:07 2009 -0800
+++ b/update_mips_ioctl_linux_call Fri Feb 06 17:32:54 2009 -0800
@@ -1,3 +1,7 @@
+From: Korey Sewell <[email protected]>
+
+syscall: Expose ioctl for MIPS
+
diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh
--- a/src/arch/mips/linux/linux.hh
+++ b/src/arch/mips/linux/linux.hh
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