changeset d3fea0b4646c in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=d3fea0b4646c
description:
Rename mixie to inorder
diffstat:
3 files changed, 1185 insertions(+), 1185 deletions(-)
import_mixie | 2364 +++++++++++++++++++++----------------------
make_mixie_cmdline_runnable | 4
prepare_cpus.diff | 2
diffs (truncated from 5891 to 300 lines):
diff -r 40721d032036 -r d3fea0b4646c import_mixie
--- a/import_mixie Fri Feb 06 17:53:25 2009 -0800
+++ b/import_mixie Fri Feb 06 17:58:45 2009 -0800
@@ -12,13 +12,13 @@
CpuModel('O3CPU', 'o3_cpu_exec.cc',
'#include "cpu/o3/isa_specific.hh"',
{ 'CPU_exec_context': 'O3DynInst' })
-+CpuModel('MixieCPU', 'mixie_cpu_exec.cc',
-+ '#include "cpu/mixie/mixie_dyn_inst.hh"',
-+ { 'CPU_exec_context': 'MixieDynInst' })
-diff --git a/src/cpu/mixie/MixieCPU.py b/src/cpu/mixie/MixieCPU.py
-new file mode 100644
---- /dev/null
-+++ b/src/cpu/mixie/MixieCPU.py
++CpuModel('InOrderCPU', 'inorder_cpu_exec.cc',
++ '#include "cpu/inorder/inorder_dyn_inst.hh"',
++ { 'CPU_exec_context': 'InOrderDynInst' })
+diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
+new file mode 100644
+--- /dev/null
++++ b/src/cpu/inorder/InOrderCPU.py
@@ -0,0 +1,80 @@
+# Copyright (c) 2007 MIPS Technologies, Inc.
+# All rights reserved.
@@ -53,8 +53,8 @@
+from m5 import build_env
+from BaseCPU import BaseCPU
+
-+class MixieCPU(BaseCPU):
-+ type = 'MixieCPU'
++class InOrderCPU(BaseCPU):
++ type = 'InOrderCPU'
+ activity = Param.Unsigned(0, "Initial count")
+ numThreads = Param.Unsigned(1, "number of HW thread contexts")
+
@@ -100,10 +100,10 @@
+ div24RepeatRate = Param.Unsigned(1, "Repeat Rate for 24-bit Divide
Operations")
+ div32Latency = Param.Unsigned(1, "Latency for 32-bit Divide Operations")
+ div32RepeatRate = Param.Unsigned(1, "Repeat Rate for 32-bit Divide
Operations")
-diff --git a/src/cpu/mixie/MixieTrace.py b/src/cpu/mixie/MixieTrace.py
-new file mode 100644
---- /dev/null
-+++ b/src/cpu/mixie/MixieTrace.py
+diff --git a/src/cpu/inorder/InOrderTrace.py b/src/cpu/inorder/InOrderTrace.py
+new file mode 100644
+--- /dev/null
++++ b/src/cpu/inorder/InOrderTrace.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2007 MIPS Technologies, Inc.
+# All rights reserved.
@@ -137,13 +137,13 @@
+from m5.params import *
+from InstTracer import InstTracer
+
-+class MixieTrace(InstTracer):
-+ type = 'MixieTrace'
-+ cxx_class = 'Trace::MixieTrace'
-diff --git a/src/cpu/mixie/SConscript b/src/cpu/mixie/SConscript
-new file mode 100644
---- /dev/null
-+++ b/src/cpu/mixie/SConscript
++class InOrderTrace(InstTracer):
++ type = 'InOrderTrace'
++ cxx_class = 'Trace::InOrderTrace'
+diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript
+new file mode 100644
+--- /dev/null
++++ b/src/cpu/inorder/SConscript
@@ -0,0 +1,82 @@
+# -*- mode:python -*-
+
@@ -177,30 +177,30 @@
+
+Import('*')
+
-+if 'MixieCPU' in env['CPU_MODELS']:
-+ SimObject('MixieCPU.py')
-+ SimObject('MixieTrace.py')
++if 'InOrderCPU' in env['CPU_MODELS']:
++ SimObject('InOrderCPU.py')
++ SimObject('InOrderTrace.py')
+
+ TraceFlag('ResReqCount')
+ TraceFlag('FreeList')
-+ TraceFlag('MixieCachePort')
-+ TraceFlag('MixieStage')
-+ TraceFlag('MixieStall')
-+ TraceFlag('MixieCPU')
-+ TraceFlag('MixieMDU')
++ TraceFlag('InOrderCachePort')
++ TraceFlag('InOrderStage')
++ TraceFlag('InOrderStall')
++ TraceFlag('InOrderCPU')
++ TraceFlag('InOrderMDU')
+ TraceFlag('RegDepMap')
+ TraceFlag('Rename')
-+ TraceFlag('MixieDynInst')
++ TraceFlag('InOrderDynInst')
+ TraceFlag('Resource')
+ TraceFlag('RefCount')
+
-+ CompoundFlag('MixieCPUAll', [ 'MixieStage', 'MixieStall', 'MixieCPU',
-+ 'MixieMDU', 'RegDepMap', 'Resource', 'Rename'])
++ CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall',
'InOrderCPU',
++ 'InOrderMDU', 'RegDepMap', 'Resource', 'Rename'])
+
+ Source('pipeline_traits.cc')
-+ Source('mixie_dyn_inst.cc')
-+ Source('mixie_cpu_builder.cc')
-+ Source('mixie_trace.cc')
++ Source('inorder_dyn_inst.cc')
++ Source('inorder_cpu_builder.cc')
++ Source('inorder_trace.cc')
+ Source('pipeline_stage.cc')
+ Source('first_stage.cc')
+ Source('resource.cc')
@@ -227,10 +227,10 @@
+ Source('thread_context.cc')
+ Source('cpu.cc')
+
-diff --git a/src/cpu/mixie/SConsopts b/src/cpu/mixie/SConsopts
-new file mode 100644
---- /dev/null
-+++ b/src/cpu/mixie/SConsopts
+diff --git a/src/cpu/inorder/SConsopts b/src/cpu/inorder/SConsopts
+new file mode 100644
+--- /dev/null
++++ b/src/cpu/inorder/SConsopts
@@ -0,0 +1,33 @@
+# -*- mode:python -*-
+
@@ -264,11 +264,11 @@
+
+Import('*')
+
-+all_cpu_list.append('MixieCPU')
-diff --git a/src/cpu/mixie/comm.hh b/src/cpu/mixie/comm.hh
-new file mode 100644
---- /dev/null
-+++ b/src/cpu/mixie/comm.hh
++all_cpu_list.append('InOrderCPU')
+diff --git a/src/cpu/inorder/comm.hh b/src/cpu/inorder/comm.hh
+new file mode 100644
+--- /dev/null
++++ b/src/cpu/inorder/comm.hh
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2007 MIPS Technologies, Inc.
@@ -301,15 +301,15 @@
+ *
+ */
+
-+#ifndef __CPU_MIXIE_COMM_HH__
-+#define __CPU_MIXIE_COMM_HH__
++#ifndef __CPU_INORDER_COMM_HH__
++#define __CPU_INORDER_COMM_HH__
+
+#include <vector>
+
+#include "arch/faults.hh"
+#include "arch/isa_traits.hh"
-+#include "cpu/mixie/mixie_dyn_inst.hh"
-+#include "cpu/mixie/pipeline_traits.hh"
++#include "cpu/inorder/inorder_dyn_inst.hh"
++#include "cpu/inorder/pipeline_traits.hh"
+#include "cpu/inst_seq.hh"
+#include "sim/host.hh"
+
@@ -373,11 +373,11 @@
+ bool stageUnblock[ThePipeline::NumStages][ThePipeline::MaxThreads];
+};
+
-+#endif //__CPU_MIXIE_COMM_HH__
-diff --git a/src/cpu/mixie/cpu.cc b/src/cpu/mixie/cpu.cc
-new file mode 100644
---- /dev/null
-+++ b/src/cpu/mixie/cpu.cc
++#endif //__CPU_INORDER_COMM_HH__
+diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
+new file mode 100644
+--- /dev/null
++++ b/src/cpu/inorder/cpu.cc
@@ -0,0 +1,1322 @@
+/*
+ * Copyright (c) 2007 MIPS Technologies, Inc.
@@ -416,15 +416,15 @@
+#include "cpu/simple_thread.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/base.hh"
-+#include "cpu/mixie/mixie_dyn_inst.hh"
-+#include "cpu/mixie/thread_context.hh"
-+#include "cpu/mixie/thread_state.hh"
-+#include "cpu/mixie/cpu.hh"
-+#include "params/MixieCPU.hh"
-+#include "cpu/mixie/pipeline_traits.hh"
-+#include "cpu/mixie/first_stage.hh"
-+#include "cpu/mixie/resources/resource_list.hh"
-+#include "cpu/mixie/resource_pool.hh"
++#include "cpu/inorder/inorder_dyn_inst.hh"
++#include "cpu/inorder/thread_context.hh"
++#include "cpu/inorder/thread_state.hh"
++#include "cpu/inorder/cpu.hh"
++#include "params/InOrderCPU.hh"
++#include "cpu/inorder/pipeline_traits.hh"
++#include "cpu/inorder/first_stage.hh"
++#include "cpu/inorder/resources/resource_list.hh"
++#include "cpu/inorder/resource_pool.hh"
+#include "mem/translating_port.hh"
+#include "sim/process.hh"
+//#include "sim/root.hh"
@@ -435,25 +435,25 @@
+using namespace TheISA;
+using namespace ThePipeline;
+
-+MixieCPU::TickEvent::TickEvent(MixieCPU *c)
++InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
+ : Event(CPU_Tick_Pri), cpu(c)
+{ }
+
+
+void
-+MixieCPU::TickEvent::process()
++InOrderCPU::TickEvent::process()
+{
+ cpu->tick();
+}
+
+
+const char *
-+MixieCPU::TickEvent::description()
-+{
-+ return "MixieCPU tick event";
-+}
-+
-+MixieCPU::CPUEvent::CPUEvent(MixieCPU *_cpu, CPUEventType e_type,
++InOrderCPU::TickEvent::description()
++{
++ return "InOrderCPU tick event";
++}
++
++InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
+ Fault fault, unsigned _tid, unsigned _vpe)
+ : Event(CPU_Tick_Pri), cpu(_cpu)
+{
@@ -461,7 +461,7 @@
+}
+
+void
-+MixieCPU::CPUEvent::process()
++InOrderCPU::CPUEvent::process()
+{
+ switch (cpuEventType)
+ {
@@ -505,13 +505,13 @@
+}
+
+const char *
-+MixieCPU::CPUEvent::description()
-+{
-+ return "MixieCPU event";
-+}
-+
-+void
-+MixieCPU::CPUEvent::scheduleEvent(int delay)
++InOrderCPU::CPUEvent::description()
++{
++ return "InOrderCPU event";
++}
++
++void
++InOrderCPU::CPUEvent::scheduleEvent(int delay)
+{
+ if (squashed())
+ mainEventQueue.reschedule(this,curTick + cpu->ticks(delay));
@@ -520,13 +520,13 @@
+}
+
+void
-+MixieCPU::CPUEvent::unscheduleEvent()
++InOrderCPU::CPUEvent::unscheduleEvent()
+{
+ if (scheduled())
+ squash();
+}
+
-+MixieCPU::MixieCPU(Params *params)
++InOrderCPU::InOrderCPU(Params *params)
+ : BaseCPU(params),
+ cpu_id(params->cpu_id),
+ tickEvent(this),
@@ -556,7 +556,7 @@
+
+ if (active_threads > MaxThreads) {
+ panic("Workload Size too large. Increase the 'MaxThreads'"
-+ "in your Mixie implementation or "
++ "in your InOrder implementation or "
+ "edit your workload size.");
+ }
+
@@ -578,7 +578,7 @@
_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
