changeset acbe11bbfe68 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=acbe11bbfe68
description:
Configs: Add support for the InOrder CPU model
diffstat:
6 files changed, 174 insertions(+), 151 deletions(-)
configs/common/Options.py | 1
configs/common/Simulation.py | 5
src/cpu/inorder/cpu.hh | 15 +
src/cpu/inorder/inorder_dyn_inst.cc | 10 -
src/cpu/inorder/resources/cache_unit.cc | 252 +++++++++++++++----------------
src/cpu/inorder/resources/cache_unit.hh | 42 +++--
diffs (truncated from 711 to 300 lines):
diff -r 09ab46bfa914 -r acbe11bbfe68 configs/common/Options.py
--- a/configs/common/Options.py Tue Feb 10 15:49:29 2009 -0800
+++ b/configs/common/Options.py Tue Feb 10 15:49:29 2009 -0800
@@ -29,6 +29,7 @@
# system options
parser.add_option("-d", "--detailed", action="store_true")
parser.add_option("-t", "--timing", action="store_true")
+parser.add_option("--inorder", action="store_true")
parser.add_option("-n", "--num-cpus", type="int", default=1)
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
diff -r 09ab46bfa914 -r acbe11bbfe68 configs/common/Simulation.py
--- a/configs/common/Simulation.py Tue Feb 10 15:49:29 2009 -0800
+++ b/configs/common/Simulation.py Tue Feb 10 15:49:29 2009 -0800
@@ -43,6 +43,11 @@
print "O3 CPU must be used with caches"
sys.exit(1)
class TmpClass(DerivO3CPU): pass
+ elif options.inorder:
+ if not options.caches:
+ print "InOrder CPU must be used with caches"
+ sys.exit(1)
+ class TmpClass(InOrderCPU): pass
else:
class TmpClass(AtomicSimpleCPU): pass
atomic = True
diff -r 09ab46bfa914 -r acbe11bbfe68 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Tue Feb 10 15:49:29 2009 -0800
+++ b/src/cpu/inorder/cpu.hh Tue Feb 10 15:49:29 2009 -0800
@@ -312,6 +312,13 @@
void deallocateThread(unsigned tid);
void deactivateThread(unsigned tid);
+ int
+ contextId()
+ {
+ hack_once("return a bogus context id");
+ return 0;
+ }
+
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.
*/
@@ -414,20 +421,20 @@
int width = TheISA::SingleWidth);
/** Reads a miscellaneous register. */
- MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
+ MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0);
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
- MiscReg readMiscReg(int misc_reg, unsigned tid);
+ MiscReg readMiscReg(int misc_reg, unsigned tid = 0);
/** Sets a miscellaneous register. */
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid);
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid =
0);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
- void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
+ void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0);
/** Reads a int/fp/misc reg. from another thread depending on ISA-defined
* target thread
diff -r 09ab46bfa914 -r acbe11bbfe68 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Tue Feb 10 15:49:29 2009 -0800
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Tue Feb 10 15:49:29 2009 -0800
@@ -454,9 +454,8 @@
MiscReg
InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
- return this->cpu->readMiscRegNoEffect(
- si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
- this->threadNumber);
+ int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+ return cpu->readMiscRegNoEffect(reg, this->threadNumber);
}
/** Reads a misc. register, including any side-effects the read
@@ -465,9 +464,8 @@
MiscReg
InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
{
- return this->cpu->readMiscReg(
- si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
- this->threadNumber);
+ int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+ return this->cpu->readMiscReg(reg, this->threadNumber);
}
/** Sets a misc. register. */
diff -r 09ab46bfa914 -r acbe11bbfe68 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Tue Feb 10 15:49:29 2009 -0800
+++ b/src/cpu/inorder/resources/cache_unit.cc Tue Feb 10 15:49:29 2009 -0800
@@ -43,7 +43,6 @@
using namespace TheISA;
using namespace ThePipeline;
-
Tick
CacheUnit::CachePort::recvAtomic(PacketPtr pkt)
{
@@ -80,7 +79,7 @@
}
CacheUnit::CacheUnit(string res_name, int res_id, int res_width,
- int res_latency, InOrderCPU *_cpu, ThePipeline::Params
*params)
+ int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
: Resource(res_name, res_id, res_width, res_latency, _cpu),
retryPkt(NULL), retrySlot(-1)
{
@@ -92,9 +91,8 @@
cacheBlocked = false;
}
-
Port *
-CacheUnit::getPort(const std::string &if_name, int idx)
+CacheUnit::getPort(const string &if_name, int idx)
{
if (if_name == resName)
return cachePort;
@@ -106,7 +104,7 @@
CacheUnit::getSlot(DynInstPtr inst)
{
if (!inst->validMemAddr()) {
- panic("Mem. Addr. must be set before requesting cache access.\n");
+ panic("Mem. Addr. must be set before requesting cache access\n");
}
Addr req_addr = inst->getMemAddr();
@@ -116,20 +114,19 @@
int new_slot = Resource::getSlot(inst);
- if (new_slot != -1) {
- inst->memTime = curTick;
- addrList.push_back(req_addr);
- addrMap[req_addr] = inst->seqNum;
- DPRINTF(InOrderCachePort, "[tid:%i]: [sn:%i]: Address %08p added
to dependency list.\n",
- inst->readTid(), inst->seqNum, req_addr);
- return new_slot;
- } else {
+ if (new_slot == -1)
return -1;
- }
-
+ inst->memTime = curTick;
+ addrList.push_back(req_addr);
+ addrMap[req_addr] = inst->seqNum;
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: [sn:%i]: Address %08p added to dependency list\n",
+ inst->readTid(), inst->seqNum, req_addr);
+ return new_slot;
} else {
- DPRINTF(InOrderCachePort,"Denying request because there is an
outstanding"
+ DPRINTF(InOrderCachePort,
+ "Denying request because there is an outstanding"
" request to/for addr. %08p. by [sn:%i] @ tick %i\n",
req_addr, addrMap[req_addr], inst->memTime);
return -1;
@@ -139,11 +136,12 @@
void
CacheUnit::freeSlot(int slot_num)
{
- std::vector<Addr>::iterator vect_it = find(addrList.begin(),
addrList.end(),
-
reqMap[slot_num]->inst->getMemAddr());
+ vector<Addr>::iterator vect_it = find(addrList.begin(), addrList.end(),
+ reqMap[slot_num]->inst->getMemAddr());
assert(vect_it != addrList.end());
- DPRINTF(InOrderCachePort, "[tid:%i]: Address %08p removed from dependency
list.\n",
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: Address %08p removed from dependency list\n",
reqMap[slot_num]->inst->readTid(), (*vect_it));
addrList.erase(vect_it);
@@ -158,7 +156,7 @@
ScheduleEntry* sched_entry = inst->resSched.top();
if (!inst->validMemAddr()) {
- panic("Mem. Addr. must be set before requesting cache access.\n");
+ panic("Mem. Addr. must be set before requesting cache access\n");
}
int req_size = 0;
@@ -168,23 +166,26 @@
pkt_cmd = MemCmd::ReadReq;
req_size = inst->getMemAccSize();
- DPRINTF(InOrderCachePort, "[tid:%i]: %i byte Read request from [sn:%i]
for addr %08p.\n",
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: %i byte Read request from [sn:%i] for addr %08p\n",
inst->readTid(), req_size, inst->seqNum, inst->getMemAddr());
} else if (sched_entry->cmd == InitiateWriteData) {
pkt_cmd = MemCmd::WriteReq;
req_size = inst->getMemAccSize();
-
- DPRINTF(InOrderCachePort, "[tid:%i]: %i byte Write request from
[sn:%i] for addr %08p.\n",
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: %i byte Write request from [sn:%i] for addr %08p\n",
inst->readTid(), req_size, inst->seqNum, inst->getMemAddr());
} else if (sched_entry->cmd == InitiateFetch){
pkt_cmd = MemCmd::ReadReq;
req_size = sizeof(MachInst); //@TODO: mips16e
- DPRINTF(InOrderCachePort, "[tid:%i]: %i byte Fetch request from
[sn:%i] for addr %08p.\n",
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: %i byte Fetch request from [sn:%i] for addr %08p\n",
inst->readTid(), req_size, inst->seqNum, inst->getMemAddr());
} else {
- panic("%i: Unexpected request type (%i) to %s", curTick,
sched_entry->cmd, name());
+ panic("%i: Unexpected request type (%i) to %s", curTick,
+ sched_entry->cmd, name());
}
return new CacheRequest(this, inst, stage_num, id, slot_num,
@@ -205,26 +206,27 @@
if (cache_req->cmd != inst->resSched.top()->cmd) {
// If different, then update command in the request
cache_req->cmd = inst->resSched.top()->cmd;
- DPRINTF(InOrderCachePort, "[tid:%i]: [sn:%i]: Updating the command for
this "
- "instruction.\n", inst->readTid(), inst->seqNum);
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: [sn:%i]: the command for this instruction\n",
+ inst->readTid(), inst->seqNum);
service_request = true;
} else {
// If same command, just check to see if memory access was completed
// but dont try to re-execute
- DPRINTF(InOrderCachePort, "[tid:%i]: [sn:%i]: requesting this resource
again.\n",
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: [sn:%i]: requesting this resource again\n",
inst->readTid(), inst->seqNum);
service_request = true;
}
-
}
void
CacheUnit::execute(int slot_num)
{
if (cacheBlocked) {
- DPRINTF(InOrderCachePort, "Cache Blocked. Cannot Access.\n");
+ DPRINTF(InOrderCachePort, "Cache Blocked. Cannot Access\n");
return;
}
@@ -243,89 +245,85 @@
switch (cache_req->cmd)
{
case InitiateFetch:
- {
- DPRINTF(InOrderCachePort,
- "[tid:%u]: Initiating fetch access to %s for addr. %08p\n",
- tid, name(), cache_req->inst->getMemAddr());
+ DPRINTF(InOrderCachePort,
+ "[tid:%u]: Initiating fetch access to %s for addr. %08p\n",
+ tid, name(), cache_req->inst->getMemAddr());
- DPRINTF(InOrderCachePort,
- "[tid:%u]: Fetching new cache block from addr: %08p\n",
- tid, cache_req->memReq->getVaddr());
+ DPRINTF(InOrderCachePort,
+ "[tid:%u]: Fetching new cache block from addr: %08p\n",
+ tid, cache_req->memReq->getVaddr());
- inst->setCurResSlot(slot_num);
- doDataAccess(inst);
- }
+ inst->setCurResSlot(slot_num);
+ doDataAccess(inst);
break;
case CompleteFetch:
- {
- if (cache_req->isMemAccComplete()) {
- DPRINTF(InOrderCachePort,
- "[tid:%i]: Completing Fetch Access for [sn:%i]\n",
- tid, inst->seqNum);
+ if (cache_req->isMemAccComplete()) {
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: Completing Fetch Access for [sn:%i]\n",
+ tid, inst->seqNum);
- MachInst mach_inst = cache_req->dataPkt->get<MachInst>();
+ MachInst mach_inst = cache_req->dataPkt->get<MachInst>();
- //@TODO: May Need This Function for Endianness-Compatibility
- //mach_inst = gtoh(*reinterpret_cast<MachInst
*>(&cacheData[tid][offset]));
+ /**
+ * @TODO: May Need This Function for Endianness-Compatibility
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