Thanks :-) On Wed, Feb 18, 2009 at 11:37 AM, Nathan Binkert <[email protected]> wrote:
> changeset e9f9c0f7e5f0 in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=e9f9c0f7e5f0 > description: > events: Make trace events happen at the right priority. > Also, while we're at it, remember that priorities are in the Event > class > and add a disable method to disable tracing. > > diffstat: > > 3 files changed, 9 insertions(+), 3 deletions(-) > src/python/m5/event.py | 7 +++++-- > src/python/m5/main.py | 2 +- > src/python/m5/trace.py | 3 +++ > > diffs (47 lines): > > diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/event.py > --- a/src/python/m5/event.py Tue Feb 17 19:24:46 2009 -0800 > +++ b/src/python/m5/event.py Wed Feb 18 10:00:15 2009 -0800 > @@ -35,13 +35,16 @@ > > def create(obj, priority=None): > if priority is None: > - priority = internal.event.Event.Default_Pri > + priority = Event.Default_Pri > return PythonEvent(obj, priority) > > + > +# As a reminder, priorities found in sim/eventq.hh are stuck into the > +# Event class by swig > class Event(PythonEvent): > def __init__(self, priority=None): > if priority is None: > - priority = internal.event.Event.Default_Pri > + priority = Event.Default_Pri > super(Event, self).__init__(self, priority) > > class ProgressEvent(Event): > diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/main.py > --- a/src/python/m5/main.py Tue Feb 17 19:24:46 2009 -0800 > +++ b/src/python/m5/main.py Wed Feb 18 10:00:15 2009 -0800 > @@ -312,7 +312,7 @@ > > if options.trace_start: > check_tracing() > - e = event.create(trace.enable) > + e = event.create(trace.enable, Event.Trace_Enable_Pri) > event.mainq.schedule(e, options.trace_start) > else: > trace.enable() > diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/trace.py > --- a/src/python/m5/trace.py Tue Feb 17 19:24:46 2009 -0800 > +++ b/src/python/m5/trace.py Wed Feb 18 10:00:15 2009 -0800 > @@ -32,6 +32,9 @@ > > from internal.trace import clear, output, set, ignore > > +def disable(): > + internal.trace.cvar.enabled = False > + > def enable(): > internal.trace.cvar.enabled = True > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev >
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