changeset 73c0aaaaf186 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=73c0aaaaf186
description:
X86: Pass whether an access was a read/write/fetch so faults can behave
accordingly.
diffstat:
6 files changed, 21 insertions(+), 12 deletions(-)
src/arch/x86/faults.cc | 4 ++--
src/arch/x86/faults.hh | 12 ++++++++----
src/arch/x86/pagetable_walker.cc | 4 +++-
src/arch/x86/pagetable_walker.hh | 5 ++++-
src/arch/x86/tlb.cc | 6 +++---
src/arch/x86/tlb.hh | 2 +-
diffs (129 lines):
diff -r 6fd7648e1b8d -r 73c0aaaaf186 src/arch/x86/faults.cc
--- a/src/arch/x86/faults.cc Fri Feb 20 11:02:48 2009 -0500
+++ b/src/arch/x86/faults.cc Mon Feb 23 00:20:34 2009 -0800
@@ -166,13 +166,13 @@
void FakeITLBFault::invoke(ThreadContext * tc)
{
// Start the page table walker.
- tc->getITBPtr()->walk(tc, vaddr);
+ tc->getITBPtr()->walk(tc, vaddr, write, execute);
}
void FakeDTLBFault::invoke(ThreadContext * tc)
{
// Start the page table walker.
- tc->getDTBPtr()->walk(tc, vaddr);
+ tc->getDTBPtr()->walk(tc, vaddr, write, execute);
}
#else // !FULL_SYSTEM
diff -r 6fd7648e1b8d -r 73c0aaaaf186 src/arch/x86/faults.hh
--- a/src/arch/x86/faults.hh Fri Feb 20 11:02:48 2009 -0500
+++ b/src/arch/x86/faults.hh Mon Feb 23 00:20:34 2009 -0800
@@ -429,10 +429,12 @@
{
protected:
Addr vaddr;
+ bool write;
+ bool execute;
public:
- FakeITLBFault(Addr _vaddr) :
+ FakeITLBFault(Addr _vaddr, bool _write, bool _execute) :
X86Fault("fake instruction tlb fault", "itlb", 0),
- vaddr(_vaddr)
+ vaddr(_vaddr), write(_write), execute(_execute)
{}
void invoke(ThreadContext * tc);
@@ -442,10 +444,12 @@
{
protected:
Addr vaddr;
+ bool write;
+ bool execute;
public:
- FakeDTLBFault(Addr _vaddr) :
+ FakeDTLBFault(Addr _vaddr, bool _write, bool _execute) :
X86Fault("fake data tlb fault", "dtlb", 0),
- vaddr(_vaddr)
+ vaddr(_vaddr), write(_write), execute(_execute)
{}
void invoke(ThreadContext * tc);
diff -r 6fd7648e1b8d -r 73c0aaaaf186 src/arch/x86/pagetable_walker.cc
--- a/src/arch/x86/pagetable_walker.cc Fri Feb 20 11:02:48 2009 -0500
+++ b/src/arch/x86/pagetable_walker.cc Mon Feb 23 00:20:34 2009 -0800
@@ -319,11 +319,13 @@
}
void
-Walker::start(ThreadContext * _tc, Addr vaddr)
+Walker::start(ThreadContext * _tc, Addr vaddr, bool _write, bool _execute)
{
assert(state == Ready);
assert(!tc);
tc = _tc;
+ execute = _execute;
+ write = _write;
VAddr addr = vaddr;
diff -r 6fd7648e1b8d -r 73c0aaaaf186 src/arch/x86/pagetable_walker.hh
--- a/src/arch/x86/pagetable_walker.hh Fri Feb 20 11:02:48 2009 -0500
+++ b/src/arch/x86/pagetable_walker.hh Mon Feb 23 00:20:34 2009 -0800
@@ -95,7 +95,7 @@
void doNext(PacketPtr &read, PacketPtr &write);
// Kick off the state machine.
- void start(ThreadContext * _tc, Addr vaddr);
+ void start(ThreadContext * _tc, Addr vaddr, bool write, bool execute);
protected:
@@ -165,7 +165,10 @@
State nextState;
int size;
bool enableNX;
+ bool write, execute;
TlbEntry entry;
+
+ Fault pageFault(bool present);
public:
diff -r 6fd7648e1b8d -r 73c0aaaaf186 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Fri Feb 20 11:02:48 2009 -0500
+++ b/src/arch/x86/tlb.cc Mon Feb 23 00:20:34 2009 -0800
@@ -140,9 +140,9 @@
#if FULL_SYSTEM
void
-TLB::walk(ThreadContext * _tc, Addr vaddr)
+TLB::walk(ThreadContext * _tc, Addr vaddr, bool write, bool execute)
{
- walker->start(_tc, vaddr);
+ walker->start(_tc, vaddr, write, execute);
}
#endif
@@ -616,7 +616,7 @@
// The vaddr already has the segment base applied.
TlbEntry *entry = lookup(vaddr);
if (!entry) {
- return new TlbFault(vaddr);
+ return new TlbFault(vaddr, write, execute);
} else {
// Do paging protection checks.
DPRINTF(TLB, "Entry found with paddr %#x, doing protection
checks.\n", entry->paddr);
diff -r 6fd7648e1b8d -r 73c0aaaaf186 src/arch/x86/tlb.hh
--- a/src/arch/x86/tlb.hh Fri Feb 20 11:02:48 2009 -0500
+++ b/src/arch/x86/tlb.hh Mon Feb 23 00:20:34 2009 -0800
@@ -119,7 +119,7 @@
Walker * walker;
- void walk(ThreadContext * _tc, Addr vaddr);
+ void walk(ThreadContext * _tc, Addr vaddr, bool write, bool execute);
#endif
public:
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