changeset c24a1ffc4ad0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c24a1ffc4ad0
description:
X86: Implement the sysret instruction in long mode.
diffstat:
2 files changed, 79 insertions(+), 5 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa | 12 ++
src/arch/x86/isa/insts/general_purpose/system_calls.py | 72 +++++++++++++++-
diffs (108 lines):
diff -r 8a633e6a8df1 -r c24a1ffc4ad0
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Wed Feb 25 10:17:49
2009 -0800
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Wed Feb 25 10:17:54
2009 -0800
@@ -265,9 +265,15 @@
0x05: SyscallInst::syscall('xc->syscall(Rax)', IsSyscall);
#endif
0x06: clts();
- //sandpile.org says (AMD) after sysret, so I might want to
check
- //if that means amd64 or AMD machines
- 0x07: loadall_or_sysret();
+ 0x07: decode MODE_SUBMODE {
+ 0x0: decode OPSIZE {
+ // Return to 64 bit mode.
+ 0x8: Inst::SYSRET_TO_64();
+ // Return to compatibility mode.
+ default: Inst::SYSRET_TO_COMPAT();
+ }
+ default: Inst::SYSRET_NON_64();
+ }
}
0x01: decode OPCODE_OP_BOTTOM3 {
0x0: invd();
diff -r 8a633e6a8df1 -r c24a1ffc4ad0
src/arch/x86/isa/insts/general_purpose/system_calls.py
--- a/src/arch/x86/isa/insts/general_purpose/system_calls.py Wed Feb 25
10:17:49 2009 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/system_calls.py Wed Feb 25
10:17:54 2009 -0800
@@ -156,12 +156,80 @@
{
panic "The syscall instruction isn't implemented in legacy mode."
};
+
+def macroop SYSRET_TO_64
+{
+ # All 1s.
+ limm t1, "(uint64_t)(-1)"
+
+ rdval t3, star
+ srli t3, t3, 48, dataSize=8
+ ori t3, t3, 3, dataSize=1
+
+ # Set rflags to r11 with RF and VM cleared.
+ limm t4, "~(RFBit | VMBit)"
+ and t4, t4, r11, dataSize=8
+ wrflags t4, t0
+
+ # Set up CS.
+ addi t4, t3, 16, dataSize=8
+ wrsel cs, t4
+ wrbase cs, t0, dataSize=8
+ wrlimit cs, t1, dataSize=4
+ # Not writable, read/execute-able, not expandDown,
+ # dpl=3, defaultSize=0, long mode
+ limm t4, ((0 << 0) | (1 << 1) | (0 << 2) | \
+ (3 << 3) | (0 << 5) | (1 << 6))
+ wrattr cs, t4
+
+ # Only the selector is changed for SS.
+ addi t4, t3, 8, dataSize=8
+ wrsel ss, t4
+
+ # Set the RIP back.
+ wrip rcx, t0, dataSize=8
+};
+
+def macroop SYSRET_TO_COMPAT
+{
+ # All 1s.
+ limm t1, "(uint64_t)(-1)"
+
+ rdval t3, star
+ srli t3, t3, 48, dataSize=8
+ ori t3, t3, 3, dataSize=1
+
+ # Set rflags to r11 with RF and VM cleared.
+ limm t4, "~(RFBit | VMBit)"
+ and t4, t4, r11, dataSize=8
+ wrflags t4, t0
+
+ # Set up CS.
+ wrsel cs, t3
+ wrbase cs, t0, dataSize=8
+ wrlimit cs, t1, dataSize=4
+ # Not writable, read/execute-able, not expandDown,
+ # dpl=3, defaultSize=1, not long mode
+ limm t4, ((0 << 0) | (1 << 1) | (0 << 2) | \
+ (3 << 3) | (1 << 5) | (0 << 6))
+ wrattr cs, t4
+
+ # Only the selector is changed for SS.
+ addi t4, t3, 8, dataSize=8
+ wrsel ss, t4
+
+ # Set the RIP back.
+ wrip rcx, t0, dataSize=8
+};
+
+def macroop SYSRET_NON_64
+{
+ panic "The sysret instruction isn't implemented in legacy mode."
+};
'''
#let {{
# class SYSENTER(Inst):
# "GenFault ${new UnimpInstFault}"
# class SYSEXIT(Inst):
# "GenFault ${new UnimpInstFault}"
-# class SYSRET(Inst):
-# "GenFault ${new UnimpInstFault}"
#}};
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
