Ok, just making sure. Congratulations on the paper Ali! :) Gabe
Steve Reinhardt wrote: > It's extremely useful... I've been leaning on Ali to get this > committed so that we can use it at AMD. I predict that some people > will switch to M5 just so they can use these features. You should > read Ali's forthcoming ISCA paper (hurrah!) to see just how cool this > is... I'll send you a copy off list. > > Steve > > On Thu, Feb 26, 2009 at 4:32 PM, Gabe Black <[email protected]> wrote: > >> Should this stuff be in the head? Is it useful outside of your project? >> >> Gabe >> >> Ali Saidi wrote: >> >>> changeset 2b989b925c9c in /z/repo/m5 >>> details: http://repo.m5sim.org/m5?cmd=changeset;node=2b989b925c9c >>> description: >>> CPA: Add annotations to IGbE and CopyEngine device models. >>> >>> diffstat: >>> >>> 4 files changed, 227 insertions(+), 5 deletions(-) >>> src/dev/copy_engine.cc | 17 ++++++++ >>> src/dev/copy_engine.hh | 30 +++++++++++++++ >>> src/dev/i8254xGBe.cc | 92 >>> +++++++++++++++++++++++++++++++++++++++++++++++ >>> src/dev/i8254xGBe.hh | 93 >>> +++++++++++++++++++++++++++++++++++++++++++++--- >>> >>> diffs (truncated from 715 to 300 lines): >>> >>> diff -r 899ecfbce5af -r 2b989b925c9c src/dev/copy_engine.cc >>> --- a/src/dev/copy_engine.cc Thu Feb 26 19:29:17 2009 -0500 >>> +++ b/src/dev/copy_engine.cc Thu Feb 26 19:29:17 2009 -0500 >>> @@ -34,6 +34,7 @@ >>> >>> #include <algorithm> >>> >>> +#include "base/cp_annotate.hh" >>> #include "base/trace.hh" >>> #include "dev/copy_engine.hh" >>> #include "mem/packet.hh" >>> @@ -427,6 +428,8 @@ >>> void >>> CopyEngine::CopyEngineChannel::fetchDescriptor(Addr address) >>> { >>> + anDq(); >>> + anBegin("FetchDescriptor"); >>> DPRINTF(DMACopyEngine, "Reading descriptor from at memory location >>> %#x(%#x)\n", >>> address, ce->platform->pciToDma(address)); >>> assert(address); >>> @@ -455,6 +458,8 @@ >>> if (inDrain()) return; >>> writeCompletionStatus(); >>> } else { >>> + anBegin("Idle"); >>> + anWait(); >>> busy = false; >>> nextState = Idle; >>> inDrain(); >>> @@ -473,6 +478,7 @@ >>> void >>> CopyEngine::CopyEngineChannel::readCopyBytes() >>> { >>> + anBegin("ReadCopyBytes"); >>> DPRINTF(DMACopyEngine, "Reading %d bytes from buffer to memory >>> location %#x(%#x)\n", >>> curDmaDesc->len, curDmaDesc->dest, >>> ce->platform->pciToDma(curDmaDesc->src)); >>> @@ -493,6 +499,7 @@ >>> void >>> CopyEngine::CopyEngineChannel::writeCopyBytes() >>> { >>> + anBegin("WriteCopyBytes"); >>> DPRINTF(DMACopyEngine, "Writing %d bytes from buffer to memory >>> location %#x(%#x)\n", >>> curDmaDesc->len, curDmaDesc->dest, >>> ce->platform->pciToDma(curDmaDesc->dest)); >>> @@ -513,6 +520,8 @@ >>> cr.status.compl_desc_addr(lastDescriptorAddr >> 6); >>> completionDataReg = cr.status() | 1; >>> >>> + anQ("DMAUsedDescQ", channelId, 1); >>> + anQ("AppRecvQ", curDmaDesc->user1, curDmaDesc->len); >>> if (curDmaDesc->command & DESC_CTRL_CP_STS) { >>> nextState = CompletionWrite; >>> if (inDrain()) return; >>> @@ -529,6 +538,8 @@ >>> busy = false; >>> >>> if (underReset) { >>> + anBegin("Reset"); >>> + anWait(); >>> underReset = false; >>> refreshNext = false; >>> busy = false; >>> @@ -549,12 +560,15 @@ >>> } else { >>> inDrain(); >>> nextState = Idle; >>> + anWait(); >>> + anBegin("Idle"); >>> } >>> } >>> >>> void >>> CopyEngine::CopyEngineChannel::writeCompletionStatus() >>> { >>> + anBegin("WriteCompletionStatus"); >>> DPRINTF(DMACopyEngine, "Writing completion status %#x to address >>> %#x(%#x)\n", >>> completionDataReg, cr.completionAddr, >>> ce->platform->pciToDma(cr.completionAddr)); >>> @@ -574,6 +588,7 @@ >>> void >>> CopyEngine::CopyEngineChannel::fetchNextAddr(Addr address) >>> { >>> + anBegin("FetchNextAddr"); >>> DPRINTF(DMACopyEngine, "Fetching next address...\n"); >>> busy = true; >>> cePort->dmaAction(MemCmd::ReadReq, ce->platform->pciToDma(address + >>> @@ -590,6 +605,8 @@ >>> DPRINTF(DMACopyEngine, "Got NULL descriptor, nothing more to >>> do\n"); >>> busy = false; >>> nextState = Idle; >>> + anWait(); >>> + anBegin("Idle"); >>> inDrain(); >>> return; >>> } >>> diff -r 899ecfbce5af -r 2b989b925c9c src/dev/copy_engine.hh >>> --- a/src/dev/copy_engine.hh Thu Feb 26 19:29:17 2009 -0500 >>> +++ b/src/dev/copy_engine.hh Thu Feb 26 19:29:17 2009 -0500 >>> @@ -130,6 +130,36 @@ >>> void recvCommand(); >>> bool inDrain(); >>> void restartStateMachine(); >>> + inline void anBegin(const char *s) >>> + { >>> + CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys, >>> + channelId, "CopyEngine", s); >>> + } >>> + >>> + inline void anWait() >>> + { >>> + CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys, >>> + channelId, "CopyEngine", "DMAUnusedDescQ", channelId); >>> + } >>> + >>> + inline void anDq() >>> + { >>> + CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys, >>> + channelId, "CopyEngine", "DMAUnusedDescQ", >>> channelId); >>> + } >>> + >>> + inline void anPq() >>> + { >>> + CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys, >>> + channelId, "CopyEngine", "DMAUnusedDescQ", >>> channelId); >>> + } >>> + >>> + inline void anQ(const char * s, uint64_t id, int size = 1) >>> + { >>> + CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId, >>> + "CopyEngine", s, id, NULL, size); >>> + } >>> + >>> }; >>> >>> private: >>> diff -r 899ecfbce5af -r 2b989b925c9c src/dev/i8254xGBe.cc >>> --- a/src/dev/i8254xGBe.cc Thu Feb 26 19:29:17 2009 -0500 >>> +++ b/src/dev/i8254xGBe.cc Thu Feb 26 19:29:17 2009 -0500 >>> @@ -113,10 +113,20 @@ >>> // Magic happy checksum value >>> flash[EEPROM_SIZE-1] = htobe((uint16_t)(EEPROM_CSUM - csum)); >>> >>> + // Store the MAC address as queue ID >>> + macAddr = p->hardware_address; >>> + >>> rxFifo.clear(); >>> txFifo.clear(); >>> } >>> >>> +void >>> +IGbE::init() >>> +{ >>> + cpa = CPA::cpa(); >>> + PciDev::init(); >>> +} >>> + >>> EtherInt* >>> IGbE::getEthPort(const std::string &if_name, int idx) >>> { >>> @@ -793,6 +803,13 @@ >>> pktEvent(this), pktHdrEvent(this), pktDataEvent(this) >>> >>> { >>> + annSmFetch = "RX Desc Fetch"; >>> + annSmWb = "RX Desc Writeback"; >>> + annUnusedDescQ = "RX Unused Descriptors"; >>> + annUnusedCacheQ = "RX Unused Descriptor Cache"; >>> + annUsedCacheQ = "RX Used Descriptor Cache"; >>> + annUsedDescQ = "RX Used Descriptors"; >>> + annDescQ = "RX Descriptors"; >>> } >>> >>> void >>> @@ -910,6 +927,8 @@ >>> RxDesc *desc; >>> desc = unusedCache.front(); >>> >>> + igbe->anBegin("RXS", "Update Desc"); >>> + >>> uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ; >>> DPRINTF(EthernetDesc, "pktPtr->length: %d bytesCopied: %d stripcrc >>> offset: %d value written: %d %d\n", >>> pktPtr->length, bytesCopied, crcfixup, >>> @@ -1052,8 +1071,11 @@ >>> enableSm(); >>> pktDone = true; >>> >>> + igbe->anBegin("RXS", "Done Updating Desc"); >>> DPRINTF(EthernetDesc, "Processing of this descriptor complete\n"); >>> + igbe->anDq("RXS", annUnusedCacheQ); >>> unusedCache.pop_front(); >>> + igbe->anQ("RXS", annUsedCacheQ); >>> usedCache.push_back(desc); >>> } >>> >>> @@ -1112,6 +1134,13 @@ >>> useTso(false), pktEvent(this), headerEvent(this), nullEvent(this) >>> >>> { >>> + annSmFetch = "TX Desc Fetch"; >>> + annSmWb = "TX Desc Writeback"; >>> + annUnusedDescQ = "TX Unused Descriptors"; >>> + annUnusedCacheQ = "TX Unused Descriptor Cache"; >>> + annUsedCacheQ = "TX Used Descriptor Cache"; >>> + annUsedDescQ = "TX Used Descriptors"; >>> + annDescQ = "TX Descriptors"; >>> } >>> >>> void >>> @@ -1154,7 +1183,9 @@ >>> >>> TxdOp::setDd(desc); >>> unusedCache.pop_front(); >>> + igbe->anDq("TXS", annUnusedCacheQ); >>> usedCache.push_back(desc); >>> + igbe->anQ("TXS", annUsedCacheQ); >>> } >>> >>> if (!unusedCache.size()) >>> @@ -1298,6 +1329,8 @@ >>> assert(unusedCache.size()); >>> assert(pktPtr); >>> >>> + igbe->anBegin("TXS", "Update Desc"); >>> + >>> DPRINTF(EthernetDesc, "DMA of packet complete\n"); >>> >>> >>> @@ -1323,7 +1356,9 @@ >>> (pktPtr->length < ( tsoMss + tsoHeaderLen) && >>> tsoTotalLen != tsoUsedLen && useTso)) { >>> assert(!useTso || (tsoDescBytesUsed == TxdOp::getLen(desc))); >>> + igbe->anDq("TXS", annUnusedCacheQ); >>> unusedCache.pop_front(); >>> + igbe->anQ("TXS", annUsedCacheQ); >>> usedCache.push_back(desc); >>> >>> tsoDescBytesUsed = 0; >>> @@ -1441,7 +1476,9 @@ >>> >>> if (!useTso || TxdOp::getLen(desc) == tsoDescBytesUsed) { >>> DPRINTF(EthernetDesc, "Descriptor Done\n"); >>> + igbe->anDq("TXS", annUnusedCacheQ); >>> unusedCache.pop_front(); >>> + igbe->anQ("TXS", annUsedCacheQ); >>> usedCache.push_back(desc); >>> tsoDescBytesUsed = 0; >>> } >>> @@ -1458,14 +1495,17 @@ >>> tsoPktHasHeader = false; >>> >>> if (igbe->regs.txdctl.wthresh() == 0) { >>> + igbe->anBegin("TXS", "Desc Writeback"); >>> DPRINTF(EthernetDesc, "WTHRESH == 0, writing back descriptor\n"); >>> writeback(0); >>> } else if (igbe->regs.txdctl.gran() && igbe->regs.txdctl.wthresh() >= >>> descInBlock(usedCache.size())) { >>> DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n"); >>> + igbe->anBegin("TXS", "Desc Writeback"); >>> writeback((igbe->cacheBlockSize()-1)>>4); >>> } else if (igbe->regs.txdctl.wthresh() >= usedCache.size()) { >>> DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n"); >>> + igbe->anBegin("TXS", "Desc Writeback"); >>> writeback((igbe->cacheBlockSize()-1)>>4); >>> } >>> >>> @@ -1604,6 +1644,7 @@ >>> else >>> changeState(Drained); >>> >>> + DPRINTF(EthernetSM, "got drain() returning %d", count); >>> return count; >>> } >>> >>> @@ -1617,6 +1658,7 @@ >>> rxTick = true; >>> >>> restartClock(); >>> + DPRINTF(EthernetSM, "resuming from drain"); >>> } >>> >>> void >>> @@ -1625,6 +1667,7 @@ >>> if (!drainEvent) >>> return; >>> >>> + DPRINTF(EthernetSM, "checkDrain() in drain\n"); >>> txFifoTick = false; >>> txTick = false; >>> rxTick = false; >>> @@ -1651,11 +1694,13 @@ >>> && !txDescCache.packetMultiDesc() && txPacket->length) { >>> bool success; >>> >>> + anQ("TXS", "TX FIFO Q"); >>> DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n"); >>> success = txFifo.push(txPacket); >>> txFifoTick = true && !drainEvent; >>> assert(success); >>> txPacket = NULL; >>> _______________________________________________ >>> m5-dev mailing list >>> [email protected] >>> http://m5sim.org/mailman/listinfo/m5-dev >>> >>> >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> >> > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
