That depends on what's on the disk image. If it's a 64 bit uniprocessor Linux kernel, it will likely almost work, or possibly actually work. If it's any other OS I don't know what will happen since I haven't tried it myself. In M5, CPU models are not generally for one ISA or another. Theoretically, you should be able to plug any ISA into any CPU model we have and it should work. In reality, the simple atomic CPU model supports x86 the best, followed by the simple timing CPU. We have two other main CPU models as well, but those need work before they support x86. We have a TLB for each ISA which behaves like you would expect a TLB to in each case, as well as a common memory system which simulates timing, caches, various coherence protocols, etc. The TLB for x86 uses a simple idealized LRU replacement policy, but it wouldn't be hard, relatively speaking, to replace that with whatever you wanted.
The other M5 developers can probably give you a better picture of how accurate the various CPU models are, what the memory system simulates, etc. Gabe Girish Venkatasubramanian wrote: > Hello Gabe, > Thanks for the reply. I have used Simics for booting a disk image and > running workloads for the X86 architecture and I would like to try the > same on M5. I have a few questions regarding this. > 1) Is M5 currently capable of doing this? > 2) Is the X86 processor model cycle accurate? > 3) If the answers to bot the above questions are No - then this > question i smoot. Otherwise, how does the X86 cpu model simulate > memory hierarchy timing - specifically TLBs and the caches - in terms > of lookup and replacement functionality? > Thanks, > Girish > > >> Date: Sat, 07 Mar 2009 10:55:19 -0800 >> From: Gabe Black <gbl...@eecs.umich.edu> >> Subject: Re: [m5-dev] X86 support >> To: M5 Developer List <m5-dev@m5sim.org> >> Message-ID: <49b2c317.5050...@eecs.umich.edu> >> Content-Type: text/plain; charset=ISO-8859-1 >> >> Hi Girish. We don't have a specific date in mind when we'll consider X86 >> finished, at least not yet. Almost all of the work we've done on it is >> available in our repositories though, and while it can't do everything >> it does support a lot. If you can describe what you need I could give >> you a better idea of what to expect. >> >> Gabe >> >> Girish Venkatasubramanian wrote: >> >>> Hello, >>> I am Girish, a grad student from University of Florida. I came across >>> M5 and found it very interesting. I am interested in trying out M5 to >>> see if I can use that for my work. >>> >>> One question - I see from the Main Page that support for X86 is under >>> development. Do you have a target date for releasing this model? >>> Thanks, >>> Girish >>> > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
