changeset 76890d8b28f5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=76890d8b28f5
description:
arm: add ARM support to M5
diffstat:
51 files changed, 8822 insertions(+)
src/arch/arm/ArmTLB.py | 58 ++
src/arch/arm/SConscript | 61 ++
src/arch/arm/SConsopts | 33 +
src/arch/arm/faults.cc | 515 ++++++++++++++++++++
src/arch/arm/faults.hh | 574 ++++++++++++++++++++++
src/arch/arm/isa/base.isa | 87 +++
src/arch/arm/isa/bitfields.isa | 170 ++++++
src/arch/arm/isa/copyright.txt | 28 +
src/arch/arm/isa/decoder.isa | 845 +++++++++++++++++++++++++++++++++
src/arch/arm/isa/formats/basic.isa | 103 ++++
src/arch/arm/isa/formats/branch.isa | 307 +++++++++++
src/arch/arm/isa/formats/formats.isa | 57 ++
src/arch/arm/isa/formats/fp.isa | 150 +++++
src/arch/arm/isa/formats/macromem.isa | 389 +++++++++++++++
src/arch/arm/isa/formats/mem.isa | 593 +++++++++++++++++++++++
src/arch/arm/isa/formats/pred.isa | 402 +++++++++++++++
src/arch/arm/isa/formats/unimp.isa | 144 +++++
src/arch/arm/isa/formats/unknown.isa | 84 +++
src/arch/arm/isa/formats/util.isa | 217 ++++++++
src/arch/arm/isa/includes.isa | 82 +++
src/arch/arm/isa/main.isa | 63 ++
src/arch/arm/isa/operands.isa | 72 ++
src/arch/arm/isa/util.isa | 282 +++++++++++
src/arch/arm/isa_traits.hh | 158 ++++++
src/arch/arm/linux/linux.cc | 73 ++
src/arch/arm/linux/linux.hh | 128 ++++
src/arch/arm/linux/process.cc | 434 ++++++++++++++++
src/arch/arm/linux/process.hh | 54 ++
src/arch/arm/locked_mem.hh | 64 ++
src/arch/arm/mmaped_ipr.hh | 64 ++
src/arch/arm/pagetable.cc | 78 +++
src/arch/arm/pagetable.hh | 102 +++
src/arch/arm/predecoder.hh | 103 ++++
src/arch/arm/process.cc | 158 ++++++
src/arch/arm/process.hh | 59 ++
src/arch/arm/regfile.hh | 36 +
src/arch/arm/regfile/float_regfile.hh | 181 +++++++
src/arch/arm/regfile/int_regfile.hh | 114 ++++
src/arch/arm/regfile/misc_regfile.hh | 100 +++
src/arch/arm/regfile/regfile.cc | 86 +++
src/arch/arm/regfile/regfile.hh | 203 +++++++
src/arch/arm/remote_gdb.hh | 66 ++
src/arch/arm/stacktrace.hh | 128 ++++
src/arch/arm/syscallreturn.hh | 57 ++
src/arch/arm/tlb.cc | 364 ++++++++++++++
src/arch/arm/tlb.hh | 164 ++++++
src/arch/arm/types.hh | 114 ++++
src/arch/arm/utility.cc | 201 +++++++
src/arch/arm/utility.hh | 92 +++
src/arch/arm/vtophys.cc | 66 ++
src/arch/arm/vtophys.hh | 59 ++
diffs (truncated from 9026 to 300 lines):
diff -r 7d32d7a137fd -r 76890d8b28f5 src/arch/arm/ArmTLB.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/ArmTLB.py Sun Apr 05 18:53:15 2009 -0700
@@ -0,0 +1,58 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2007-2008 The Florida State University
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Stephen Hines
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+class ArmTLB(SimObject):
+ abstract = True
+ type = 'ArmTLB'
+ cxx_namespace = 'ArmISA'
+ cxx_class = 'TLB'
+ size = Param.Int("TLB size")
+
+class ArmDTB(ArmTLB):
+ type = 'ArmDTB'
+ cxx_namespace = 'ArmISA'
+ cxx_class = 'DTB'
+ size = 64
+
+class ArmITB(ArmTLB):
+ type = 'ArmITB'
+ cxx_namespace = 'ArmISA'
+ cxx_class = 'ITB'
+ size = 64
+
+class ArmUTB(ArmTLB):
+ type = 'ArmUTB'
+ cxx_namespace = 'ArmISA'
+ cxx_class = 'UTB'
+ size = 64
+
diff -r 7d32d7a137fd -r 76890d8b28f5 src/arch/arm/SConscript
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/SConscript Sun Apr 05 18:53:15 2009 -0700
@@ -0,0 +1,61 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2007-2008 The Florida State University
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Stephen Hines
+
+Import('*')
+
+if env['TARGET_ISA'] == 'arm':
+# Workaround for bug in SCons version > 0.97d20071212
+# Scons bug id: 2006 M5 Bug id: 308
+ Dir('isa/formats')
+ Source('faults.cc')
+ Source('pagetable.cc')
+ Source('regfile/regfile.cc')
+ Source('tlb.cc')
+ Source('utility.cc')
+ Source('vtophys.cc')
+
+ SimObject('ArmTLB.py')
+ TraceFlag('Arm')
+
+ if env['FULL_SYSTEM']:
+ #Insert Full-System Files Here
+ pass
+ else:
+ Source('process.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+
+ # Add in files generated by the ISA description.
+ isa_desc_files = env.ISADesc('isa/main.isa')
+ # Only non-header files need to be compiled.
+ for f in isa_desc_files:
+ if not f.path.endswith('.hh'):
+ Source(f)
+
diff -r 7d32d7a137fd -r 76890d8b28f5 src/arch/arm/SConsopts
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/SConsopts Sun Apr 05 18:53:15 2009 -0700
@@ -0,0 +1,33 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2007-2008 The Florida State University
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Stephen Hines
+
+Import('*')
+
+all_isa_list.append('arm')
diff -r 7d32d7a137fd -r 76890d8b28f5 src/arch/arm/faults.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/faults.cc Sun Apr 05 18:53:15 2009 -0700
@@ -0,0 +1,515 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Stephen Hines
+ */
+
+#include "arch/arm/faults.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/base.hh"
+#include "base/trace.hh"
+#if !FULL_SYSTEM
+#include "sim/process.hh"
+#include "mem/page_table.hh"
+#endif
+
+namespace ArmISA
+{
+
+FaultName MachineCheckFault::_name = "Machine Check";
+FaultVect MachineCheckFault::_vect = 0x0401;
+FaultStat MachineCheckFault::_count;
+
+FaultName AlignmentFault::_name = "Alignment";
+FaultVect AlignmentFault::_vect = 0x0301;
+FaultStat AlignmentFault::_count;
+
+FaultName ResetFault::_name = "Reset Fault";
+#if FULL_SYSTEM
+FaultVect ResetFault::_vect = 0xBFC00000;
+#else
+FaultVect ResetFault::_vect = 0x001;
+#endif
+FaultStat ResetFault::_count;
+
+FaultName AddressErrorFault::_name = "Address Error";
+FaultVect AddressErrorFault::_vect = 0x0180;
+FaultStat AddressErrorFault::_count;
+
+FaultName StoreAddressErrorFault::_name = "Store Address Error";
+FaultVect StoreAddressErrorFault::_vect = 0x0180;
+FaultStat StoreAddressErrorFault::_count;
+
+
+FaultName SystemCallFault::_name = "Syscall";
+FaultVect SystemCallFault::_vect = 0x0180;
+FaultStat SystemCallFault::_count;
+
+FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault";
+FaultVect CoprocessorUnusableFault::_vect = 0x180;
+FaultStat CoprocessorUnusableFault::_count;
+
+FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault";
+FaultVect ReservedInstructionFault::_vect = 0x0180;
+FaultStat ReservedInstructionFault::_count;
+
+FaultName ThreadFault::_name = "Thread Fault";
+FaultVect ThreadFault::_vect = 0x00F1;
+FaultStat ThreadFault::_count;
+
+
+FaultName ArithmeticFault::_name = "Arithmetic Overflow Exception";
+FaultVect ArithmeticFault::_vect = 0x180;
+FaultStat ArithmeticFault::_count;
+
+FaultName UnimplementedOpcodeFault::_name = "opdec";
+FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
+FaultStat UnimplementedOpcodeFault::_count;
+
+FaultName InterruptFault::_name = "interrupt";
+FaultVect InterruptFault::_vect = 0x0180;
+FaultStat InterruptFault::_count;
+
+FaultName TrapFault::_name = "Trap";
+FaultVect TrapFault::_vect = 0x0180;
+FaultStat TrapFault::_count;
+
+FaultName BreakpointFault::_name = "Breakpoint";
+FaultVect BreakpointFault::_vect = 0x0180;
+FaultStat BreakpointFault::_count;
+
+
+FaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)";
+FaultVect ItbInvalidFault::_vect = 0x0180;
+FaultStat ItbInvalidFault::_count;
+
+FaultName ItbPageFault::_name = "itbmiss";
+FaultVect ItbPageFault::_vect = 0x0181;
+FaultStat ItbPageFault::_count;
+
+FaultName ItbMissFault::_name = "itbmiss";
+FaultVect ItbMissFault::_vect = 0x0181;
+FaultStat ItbMissFault::_count;
+
+FaultName ItbAcvFault::_name = "iaccvio";
+FaultVect ItbAcvFault::_vect = 0x0081;
+FaultStat ItbAcvFault::_count;
+
+FaultName ItbRefillFault::_name = "TLB Refill Exception (I-Fetch/LW)";
+FaultVect ItbRefillFault::_vect = 0x0180;
+FaultStat ItbRefillFault::_count;
+
+FaultName NDtbMissFault::_name = "dtb_miss_single";
+FaultVect NDtbMissFault::_vect = 0x0201;
+FaultStat NDtbMissFault::_count;
+
+FaultName PDtbMissFault::_name = "dtb_miss_double";
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
