changeset 595b5016f6d5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=595b5016f6d5
description:
X86: Implement the STARTUP IPI.
diffstat:
2 files changed, 30 insertions(+)
src/arch/x86/faults.cc | 20 ++++++++++++++++++++
src/arch/x86/faults.hh | 10 ++++++++++
diffs (50 lines):
diff -r 65a321a3a691 -r 595b5016f6d5 src/arch/x86/faults.cc
--- a/src/arch/x86/faults.cc Sun Apr 19 02:53:00 2009 -0700
+++ b/src/arch/x86/faults.cc Sun Apr 19 02:56:03 2009 -0700
@@ -282,6 +282,26 @@
tc->setNextMicroPC(romMicroPC(entry) + 1);
}
+ void
+ StartupInterrupt::invoke(ThreadContext *tc)
+ {
+ DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
+ HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
+ if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
+ panic("Startup IPI recived outside of real mode. "
+ "Don't know what to do.");
+ }
+
+ tc->setMiscReg(MISCREG_CS, vector << 8);
+ tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
+ tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
+ // This has the base value pre-added.
+ tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
+
+ tc->setPC(tc->readMiscReg(MISCREG_CS_BASE));
+ tc->setNextPC(tc->readPC() + sizeof(MachInst));
+ }
+
#endif
} // namespace X86ISA
diff -r 65a321a3a691 -r 595b5016f6d5 src/arch/x86/faults.hh
--- a/src/arch/x86/faults.hh Sun Apr 19 02:53:00 2009 -0700
+++ b/src/arch/x86/faults.hh Sun Apr 19 02:56:03 2009 -0700
@@ -418,6 +418,16 @@
void invoke(ThreadContext * tc);
};
+ class StartupInterrupt : public X86Interrupt
+ {
+ public:
+ StartupInterrupt(uint8_t _vector) :
+ X86Interrupt("Startup Interrupt", "#SIPI", _vector)
+ {}
+
+ void invoke(ThreadContext * tc);
+ };
+
class SoftwareInterrupt : public X86Interrupt
{
public:
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