changeset 0ad264b74ac2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0ad264b74ac2
description:
X86: Use recvResponse to implement the idle bit in the Local APIC ICR.
diffstat:
1 file changed, 19 insertions(+)
src/arch/x86/interrupts.cc | 19 +++++++++++++++++++
diffs (39 lines):
diff -r 46d327d42036 -r 0ad264b74ac2 src/arch/x86/interrupts.cc
--- a/src/arch/x86/interrupts.cc Sun Apr 19 03:54:11 2009 -0700
+++ b/src/arch/x86/interrupts.cc Sun Apr 19 03:56:24 2009 -0700
@@ -332,6 +332,22 @@
}
+Tick
+X86ISA::Interrupts::recvResponse(PacketPtr pkt)
+{
+ assert(!pkt->isError());
+ assert(pkt->cmd == MemCmd::MessageResp);
+ InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
+ // Record that the ICR is now idle.
+ low.deliveryStatus = 0;
+ regs[APIC_INTERRUPT_COMMAND_LOW] = low;
+ delete pkt->req;
+ delete pkt;
+ DPRINTF(LocalApic, "ICR is now idle.\n");
+ return 0;
+}
+
+
void
X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
{
@@ -475,9 +491,12 @@
message.level = low.level;
message.trigger = low.trigger;
bool timing = sys->getMemoryMode() == Enums::timing;
+ // Be careful no updates of the delivery status bit get lost.
+ regs[APIC_INTERRUPT_COMMAND_LOW] = low;
switch (low.destShorthand) {
case 0:
intPort->sendMessage(message, timing);
+ newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
break;
case 1:
panic("Self IPIs aren't implemented.\n");
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