changeset 9af6fb59752f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9af6fb59752f
description:
mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
diffstat:
17 files changed, 92 insertions(+), 94 deletions(-)
configs/common/Caches.py | 1
configs/common/FSConfig.py | 13 ++-
configs/example/fs.py | 3
src/dev/Device.py | 1
src/mem/Bus.py | 6 -
src/mem/bus.cc | 3
src/mem/cache/BaseCache.py | 8 --
src/mem/cache/base.cc | 9 +-
src/mem/cache/base.hh | 20 +++--
src/mem/cache/cache.hh | 6 -
src/mem/cache/cache_impl.hh | 92 ++++++++++++---------------
tests/configs/tsunami-o3-dual.py | 4 -
tests/configs/tsunami-o3.py | 4 -
tests/configs/tsunami-simple-atomic-dual.py | 4 -
tests/configs/tsunami-simple-atomic.py | 4 -
tests/configs/tsunami-simple-timing-dual.py | 4 -
tests/configs/tsunami-simple-timing.py | 4 -
diffs (truncated from 496 to 300 lines):
diff -r 18aff7f548c1 -r 9af6fb59752f configs/common/Caches.py
--- a/configs/common/Caches.py Tue Apr 21 17:17:16 2009 -0700
+++ b/configs/common/Caches.py Wed Jul 16 11:10:33 2008 -0700
@@ -50,3 +50,4 @@
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
+ forward_snoops = False
diff -r 18aff7f548c1 -r 9af6fb59752f configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Tue Apr 21 17:17:16 2009 -0700
+++ b/configs/common/FSConfig.py Wed Jul 16 11:10:33 2008 -0700
@@ -38,6 +38,11 @@
def childImage(self, ci):
self.image.child.image_file = ci
+class MemBus(Bus):
+ badaddr_responder = BadAddr()
+ default = Self.badaddr_responder.pio
+
+
def makeLinuxAlphaSystem(mem_mode, mdesc = None):
class BaseTsunami(Tsunami):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
@@ -50,7 +55,7 @@
mdesc = SysConfig()
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
- self.membus = Bus(bus_id=1)
+ self.membus = MemBus(bus_id=1)
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
self.bridge.side_a = self.iobus.port
@@ -90,7 +95,7 @@
mdesc = SysConfig()
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
- self.membus = Bus(bus_id=1)
+ self.membus = MemBus(bus_id=1)
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
@@ -130,7 +135,7 @@
mdesc = SysConfig()
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
- self.membus = Bus(bus_id=1)
+ self.membus = MemBus(bus_id=1)
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.physmem = PhysicalMemory(range = AddrRange('1GB'))
self.bridge.side_a = self.iobus.port
@@ -170,7 +175,7 @@
self.readfile = mdesc.script()
# Physical memory
- self.membus = Bus(bus_id=1)
+ self.membus = MemBus(bus_id=1)
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
self.physmem.port = self.membus.port
diff -r 18aff7f548c1 -r 9af6fb59752f configs/example/fs.py
--- a/configs/example/fs.py Tue Apr 21 17:17:16 2009 -0700
+++ b/configs/example/fs.py Wed Jul 16 11:10:33 2008 -0700
@@ -126,8 +126,7 @@
if options.caches:
test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
- test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
- cpu_side_filter_ranges=[AddrRange(0x8000000000,
Addr.max)])
+ test_sys.iocache = IOCache(addr_range=AddrRange(0, size='8GB'))
test_sys.iocache.cpu_side = test_sys.iobus.port
test_sys.iocache.mem_side = test_sys.membus.port
diff -r 18aff7f548c1 -r 9af6fb59752f src/dev/Device.py
--- a/src/dev/Device.py Tue Apr 21 17:17:16 2009 -0700
+++ b/src/dev/Device.py Wed Jul 16 11:10:33 2008 -0700
@@ -66,6 +66,7 @@
warn_access = Param.String("", "String to print when device is accessed")
class BadAddr(IsaFake):
+ pio_addr = 0
ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
diff -r 18aff7f548c1 -r 9af6fb59752f src/mem/Bus.py
--- a/src/mem/Bus.py Tue Apr 21 17:17:16 2009 -0700
+++ b/src/mem/Bus.py Wed Jul 16 11:10:33 2008 -0700
@@ -43,8 +43,4 @@
width = Param.Int(64, "bus width (bytes)")
responder_set = Param.Bool(False, "Did the user specify a default
responder.")
block_size = Param.Int(64, "The default block size if one isn't set by a
device attached to the bus.")
- if build_env['FULL_SYSTEM']:
- responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
- default = Port(Self.responder.pio, "Default port for requests that
aren't handled by a device.")
- else:
- default = Port("Default port for requests that aren't handled by a
device.")
+ default = Port("Default port for requests that aren't handled by a
device.")
diff -r 18aff7f548c1 -r 9af6fb59752f src/mem/bus.cc
--- a/src/mem/bus.cc Tue Apr 21 17:17:16 2009 -0700
+++ b/src/mem/bus.cc Wed Jul 16 11:10:33 2008 -0700
@@ -219,7 +219,7 @@
}
}
} else {
- assert(dest >= 0 && dest < maxId);
+ assert(dest < maxId);
assert(dest != src); // catch infinite loops
dest_port_id = dest;
if (dest_port_id == defaultId)
@@ -238,7 +238,6 @@
if (dest_port_id == src) {
// Must be forwarded snoop up from below...
assert(dest == Packet::Broadcast);
- assert(src != defaultId); // catch infinite loops
} else {
// send to actual target
if (!dest_port->sendTiming(pkt)) {
diff -r 18aff7f548c1 -r 9af6fb59752f src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.py Tue Apr 21 17:17:16 2009 -0700
+++ b/src/mem/cache/BaseCache.py Wed Jul 16 11:10:33 2008 -0700
@@ -45,6 +45,8 @@
"always service demand misses first")
repl = Param.Repl(NULL, "replacement policy")
size = Param.MemorySize("capacity in bytes")
+ forward_snoops = Param.Bool(True,
+ "forward snoops from mem side to cpu side")
subblock_size = Param.Int(0,
"Size of subblock in IIC used for compression")
tgts_per_mshr = Param.Int("max number of accesses per MSHR")
@@ -74,8 +76,4 @@
"Only prefetch on data not on instruction accesses")
cpu_side = Port("Port on side closer to CPU")
mem_side = Port("Port on side closer to MEM")
- cpu_side_filter_ranges = VectorParam.AddrRange([],
- "What addresses shouldn't be passed through the side of the
bridge")
- mem_side_filter_ranges = VectorParam.AddrRange([],
- "What addresses shouldn't be passed through the side of the
bridge")
- addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes")
+ addr_range = Param.AddrRange(AllMemory, "The address range for the
CPU-side port")
diff -r 18aff7f548c1 -r 9af6fb59752f src/mem/cache/base.cc
--- a/src/mem/cache/base.cc Tue Apr 21 17:17:16 2009 -0700
+++ b/src/mem/cache/base.cc Wed Jul 16 11:10:33 2008 -0700
@@ -41,11 +41,10 @@
using namespace std;
BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
- const std::string &_label,
- std::vector<Range<Addr> > filter_ranges)
+ const std::string &_label)
: SimpleTimingPort(_name, _cache), cache(_cache),
label(_label), otherPort(NULL),
- blocked(false), mustSendRetry(false), filterRanges(filter_ranges)
+ blocked(false), mustSendRetry(false)
{
}
@@ -58,10 +57,12 @@
blkSize(p->block_size),
hitLatency(p->latency),
numTarget(p->tgts_per_mshr),
+ forwardSnoops(p->forward_snoops),
blocked(0),
noTargetMSHR(NULL),
missCount(p->max_miss_count),
- drainEvent(NULL)
+ drainEvent(NULL),
+ addrRange(p->addr_range)
{
}
diff -r 18aff7f548c1 -r 9af6fb59752f src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Tue Apr 21 17:17:16 2009 -0700
+++ b/src/mem/cache/base.hh Wed Jul 16 11:10:33 2008 -0700
@@ -100,8 +100,7 @@
protected:
CachePort(const std::string &_name, BaseCache *_cache,
- const std::string &_label,
- std::vector<Range<Addr> > filter_ranges);
+ const std::string &_label);
virtual void recvStatusChange(Status status);
@@ -129,9 +128,6 @@
bool mustSendRetry;
- /** filter ranges */
- std::vector<Range<Addr> > filterRanges;
-
void requestBus(RequestCause cause, Tick time)
{
DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
@@ -194,8 +190,8 @@
/** The number of targets for each MSHR. */
const int numTarget;
- /** Increasing order number assigned to each incoming request. */
- uint64_t order;
+ /** Do we forward snoops from mem side port through to cpu side port? */
+ bool forwardSnoops;
/**
* Bit vector of the blocking reasons for the access path.
@@ -203,6 +199,9 @@
*/
uint8_t blocked;
+ /** Increasing order number assigned to each incoming request. */
+ uint64_t order;
+
/** Stores time the cache blocked for statistics. */
Tick blockedCycle;
@@ -215,6 +214,11 @@
/** The drain event. */
Event *drainEvent;
+ /**
+ * The address range to which the cache responds on the CPU side.
+ * Normally this is all possible memory addresses. */
+ Range<Addr> addrRange;
+
public:
// Statistics
/**
@@ -377,6 +381,8 @@
Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); }
+ const Range<Addr> &getAddrRange() const { return addrRange; }
+
MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
{
assert(!pkt->req->isUncacheable());
diff -r 18aff7f548c1 -r 9af6fb59752f src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hh Tue Apr 21 17:17:16 2009 -0700
+++ b/src/mem/cache/cache.hh Wed Jul 16 11:10:33 2008 -0700
@@ -71,8 +71,7 @@
public:
CpuSidePort(const std::string &_name,
Cache<TagStore> *_cache,
- const std::string &_label,
- std::vector<Range<Addr> > filterRanges);
+ const std::string &_label);
// BaseCache::CachePort just has a BaseCache *; this function
// lets us get back the type info we lost when we stored the
@@ -96,8 +95,7 @@
public:
MemSidePort(const std::string &_name,
Cache<TagStore> *_cache,
- const std::string &_label,
- std::vector<Range<Addr> > filterRanges);
+ const std::string &_label);
// BaseCache::CachePort just has a BaseCache *; this function
// lets us get back the type info we lost when we stored the
diff -r 18aff7f548c1 -r 9af6fb59752f src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Tue Apr 21 17:17:16 2009 -0700
+++ b/src/mem/cache/cache_impl.hh Wed Jul 16 11:10:33 2008 -0700
@@ -40,7 +40,7 @@
#include "sim/host.hh"
#include "base/fast_alloc.hh"
#include "base/misc.hh"
-#include "base/range_ops.hh"
+#include "base/range.hh"
#include "mem/cache/cache.hh"
#include "mem/cache/blk.hh"
@@ -62,11 +62,9 @@
tempBlock->data = new uint8_t[blkSize];
cpuSidePort = new CpuSidePort(p->name + "-cpu_side_port", this,
- "CpuSidePort",
- p->cpu_side_filter_ranges);
+ "CpuSidePort");
memSidePort = new MemSidePort(p->name + "-mem_side_port", this,
- "MemSidePort",
- p->mem_side_filter_ranges);
+ "MemSidePort");
cpuSidePort->setOtherPort(memSidePort);
memSidePort->setOtherPort(cpuSidePort);
@@ -96,8 +94,7 @@
} else if (if_name == "functional") {
CpuSidePort *funcPort =
new CpuSidePort(name() + "-cpu_side_funcport", this,
- "CpuSideFuncPort",
- std::vector<Range<Addr> >());
+ "CpuSideFuncPort");
funcPort->setOtherPort(memSidePort);
return funcPort;
} else {
@@ -1063,35 +1060,37 @@
assert(!(pending_inval && !is_deferred));
assert(pkt->isRequest());
- // first propagate snoop upward to see if anyone above us wants to
- // handle it. save & restore packet src since it will get
- // rewritten to be relative to cpu-side bus (if any)
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