changeset af63ab37f87c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=af63ab37f87c
description:
i8254xGBe: major style overhaul.
Moved DescCache template functions from .hh to .cc file.
Also fixed lots of line-wrapping problems, and some irregular
indentation.
diffstat:
2 files changed, 673 insertions(+), 555 deletions(-)
src/dev/i8254xGBe.cc | 840 +++++++++++++++++++++++++++++++++++++-------------
src/dev/i8254xGBe.hh | 388 ++---------------------
diffs (truncated from 1905 to 300 lines):
diff -r 82c377317a86 -r af63ab37f87c src/dev/i8254xGBe.cc
--- a/src/dev/i8254xGBe.cc Wed Apr 22 01:55:52 2009 -0400
+++ b/src/dev/i8254xGBe.cc Wed Apr 22 01:58:53 2009 -0400
@@ -55,7 +55,8 @@
using namespace Net;
IGbE::IGbE(const Params *p)
- : EtherDevice(p), etherInt(NULL), drainEvent(NULL),
useFlowControl(p->use_flow_control),
+ : EtherDevice(p), etherInt(NULL), drainEvent(NULL),
+ useFlowControl(p->use_flow_control),
rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
txTick(false), txFifoTick(false), rxDmaPacket(false), pktOffset(0),
fetchDelay(p->fetch_delay), wbDelay(p->wb_delay),
@@ -148,13 +149,16 @@
else
panic("Device specific PCI config space not implemented.\n");
- ///
- /// Some work may need to be done here based for the pci COMMAND bits.
- ///
+ //
+ // Some work may need to be done here based for the pci COMMAND bits.
+ //
return pioDelay;
}
+// Handy macro for range-testing register access addresses
+#define IN_RANGE(val, base, len) (val >= base && val < (base + len))
+
Tick
IGbE::read(PacketPtr pkt)
{
@@ -174,9 +178,9 @@
pkt->allocate();
- ///
- /// Handle read of register here
- ///
+ //
+ // Handle read of register here
+ //
switch (daddr) {
@@ -199,8 +203,8 @@
pkt->set<uint32_t>(regs.mdic());
break;
case REG_ICR:
- DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
regs.icr(),
- regs.imr, regs.iam, regs.ctrl_ext.iame());
+ DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
+ regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame());
pkt->set<uint32_t>(regs.icr());
if (regs.icr.int_assert() || regs.imr == 0) {
regs.icr = regs.icr() & ~mask(30);
@@ -262,7 +266,8 @@
pkt->set<uint32_t>(regs.rdtr());
if (regs.rdtr.fpd()) {
rxDescCache.writeback(0);
- DPRINTF(EthernetIntr, "Posting interrupt because of RDTR.FPD
write\n");
+ DPRINTF(EthernetIntr,
+ "Posting interrupt because of RDTR.FPD write\n");
postInterrupt(IT_RXT);
regs.rdtr.fpd(0);
}
@@ -329,10 +334,10 @@
pkt->set<uint32_t>(regs.sw_fw_sync);
break;
default:
- if (!(daddr >= REG_VFTA && daddr < (REG_VFTA +
VLAN_FILTER_TABLE_SIZE*4)) &&
- !(daddr >= REG_RAL && daddr < (REG_RAL +
RCV_ADDRESS_TABLE_SIZE*8)) &&
- !(daddr >= REG_MTA && daddr < (REG_MTA + MULTICAST_TABLE_SIZE*4))
&&
- !(daddr >= REG_CRCERRS && daddr < (REG_CRCERRS + STATS_REGS_SIZE)))
+ if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) &&
+ !IN_RANGE(daddr, REG_RAL, RCV_ADDRESS_TABLE_SIZE*8) &&
+ !IN_RANGE(daddr, REG_MTA, MULTICAST_TABLE_SIZE*4) &&
+ !IN_RANGE(daddr, REG_CRCERRS, STATS_REGS_SIZE))
panic("Read request to unknown register number: %#x\n", daddr);
else
pkt->set<uint32_t>(0);
@@ -358,11 +363,12 @@
// Only 32bit accesses allowed
assert(pkt->getSize() == sizeof(uint32_t));
- DPRINTF(Ethernet, "Wrote device register %#X value %#X\n", daddr,
pkt->get<uint32_t>());
+ DPRINTF(Ethernet, "Wrote device register %#X value %#X\n",
+ daddr, pkt->get<uint32_t>());
- ///
- /// Handle write of register here
- ///
+ //
+ // Handle write of register here
+ //
uint32_t val = pkt->get<uint32_t>();
Regs::RCTL oldrctl;
@@ -397,7 +403,8 @@
} else if (eeDataBits < 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
assert(eeAddr>>1 < EEPROM_SIZE);
DPRINTF(EthernetEEPROM, "EEPROM bit read: %d word: %#X\n",
- flash[eeAddr>>1] >> eeDataBits & 0x1,
flash[eeAddr>>1]);
+ flash[eeAddr>>1] >> eeDataBits & 0x1,
+ flash[eeAddr>>1]);
regs.eecd.dout((flash[eeAddr>>1] >> (15-eeDataBits)) & 0x1);
eeDataBits++;
} else if (eeDataBits < 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI) {
@@ -405,27 +412,27 @@
eeDataBits++;
} else
panic("What's going on with eeprom interface? opcode:"
- " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode,
- (uint32_t)eeOpBits, (uint32_t)eeAddr,
- (uint32_t)eeAddrBits, (uint32_t)eeDataBits);
+ " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode,
+ (uint32_t)eeOpBits, (uint32_t)eeAddr,
+ (uint32_t)eeAddrBits, (uint32_t)eeDataBits);
// Reset everything for the next command
if ((eeDataBits == 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) ||
- (eeDataBits == 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI)) {
+ (eeDataBits == 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI)) {
eeOpBits = 0;
eeAddrBits = 0;
eeDataBits = 0;
- eeOpcode = 0;
+ eeOpcode = 0;
eeAddr = 0;
}
- DPRINTF(EthernetEEPROM, "EEPROM: opcode: %#X:%d addr: %#X:%d\n",
+ DPRINTF(EthernetEEPROM, "EEPROM: opcode: %#X:%d addr: %#X:%d\n",
(uint32_t)eeOpcode, (uint32_t) eeOpBits,
(uint32_t)eeAddr>>1, (uint32_t)eeAddrBits);
- if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI ||
+ if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI ||
eeOpcode == EEPROM_RDSR_OPCODE_SPI ))
panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode,
- (uint32_t)eeOpBits);
+ (uint32_t)eeOpBits);
}
@@ -449,35 +456,36 @@
panic("No support for interrupt on mdic complete\n");
if (regs.mdic.phyadd() != 1)
panic("No support for reading anything but phy\n");
- DPRINTF(Ethernet, "%s phy address %x\n", regs.mdic.op() == 1 ?
"Writing"
- : "Reading", regs.mdic.regadd());
+ DPRINTF(Ethernet, "%s phy address %x\n",
+ regs.mdic.op() == 1 ? "Writing" : "Reading",
+ regs.mdic.regadd());
switch (regs.mdic.regadd()) {
- case PHY_PSTATUS:
- regs.mdic.data(0x796D); // link up
- break;
- case PHY_PID:
- regs.mdic.data(params()->phy_pid);
- break;
- case PHY_EPID:
- regs.mdic.data(params()->phy_epid);
- break;
- case PHY_GSTATUS:
- regs.mdic.data(0x7C00);
- break;
- case PHY_EPSTATUS:
- regs.mdic.data(0x3000);
- break;
- case PHY_AGC:
- regs.mdic.data(0x180); // some random length
- break;
- default:
- regs.mdic.data(0);
+ case PHY_PSTATUS:
+ regs.mdic.data(0x796D); // link up
+ break;
+ case PHY_PID:
+ regs.mdic.data(params()->phy_pid);
+ break;
+ case PHY_EPID:
+ regs.mdic.data(params()->phy_epid);
+ break;
+ case PHY_GSTATUS:
+ regs.mdic.data(0x7C00);
+ break;
+ case PHY_EPSTATUS:
+ regs.mdic.data(0x3000);
+ break;
+ case PHY_AGC:
+ regs.mdic.data(0x180); // some random length
+ break;
+ default:
+ regs.mdic.data(0);
}
regs.mdic.r(1);
break;
case REG_ICR:
- DPRINTF(Ethernet, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
regs.icr(),
- regs.imr, regs.iam, regs.ctrl_ext.iame());
+ DPRINTF(Ethernet, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
+ regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame());
if (regs.ctrl_ext.iame())
regs.imr &= ~regs.iam;
regs.icr = ~bits(val,30,0) & regs.icr();
@@ -490,7 +498,7 @@
DPRINTF(EthernetIntr, "Posting interrupt because of ICS write\n");
postInterrupt((IntTypes)val);
break;
- case REG_IMS:
+ case REG_IMS:
regs.imr |= val;
chkInterrupt();
break;
@@ -522,12 +530,12 @@
oldtctl = regs.tctl;
regs.tctl = val;
if (regs.tctl.en())
- txTick = true;
+ txTick = true;
restartClock();
if (regs.tctl.en() && !oldtctl.en()) {
txDescCache.reset();
}
- break;
+ break;
case REG_PBA:
regs.pba.rxa(val);
regs.pba.txa(64 - regs.pba.rxa());
@@ -632,12 +640,14 @@
case REG_TDWBAL:
regs.tdwba &= ~mask(32);
regs.tdwba |= val;
- txDescCache.completionWriteback(regs.tdwba & ~mask(1), regs.tdwba &
mask(1));
+ txDescCache.completionWriteback(regs.tdwba & ~mask(1),
+ regs.tdwba & mask(1));
break;
case REG_TDWBAH:
regs.tdwba &= mask(32);
regs.tdwba |= (uint64_t)val << 32;
- txDescCache.completionWriteback(regs.tdwba & ~mask(1), regs.tdwba &
mask(1));
+ txDescCache.completionWriteback(regs.tdwba & ~mask(1),
+ regs.tdwba & mask(1));
break;
case REG_RXCSUM:
regs.rxcsum = val;
@@ -662,10 +672,10 @@
regs.sw_fw_sync = val;
break;
default:
- if (!(daddr >= REG_VFTA && daddr < (REG_VFTA +
VLAN_FILTER_TABLE_SIZE*4)) &&
- !(daddr >= REG_RAL && daddr < (REG_RAL + RCV_ADDRESS_TABLE_SIZE*8))
&&
- !(daddr >= REG_MTA && daddr < (REG_MTA + MULTICAST_TABLE_SIZE*4)))
- panic("Write request to unknown register number: %#x\n", daddr);
+ if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) &&
+ !IN_RANGE(daddr, REG_RAL, RCV_ADDRESS_TABLE_SIZE*8) &&
+ !IN_RANGE(daddr, REG_MTA, MULTICAST_TABLE_SIZE*4))
+ panic("Write request to unknown register number: %#x\n", daddr);
};
pkt->makeAtomicResponse();
@@ -684,22 +694,24 @@
regs.icr = regs.icr() | t;
Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval();
- DPRINTF(EthernetIntr, "EINT: postInterrupt() curTick: %d itr: %d interval:
%d\n",
+ DPRINTF(EthernetIntr,
+ "EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
curTick, regs.itr.interval(), itr_interval);
- if (regs.itr.interval() == 0 || now || lastInterrupt + itr_interval <=
curTick) {
+ if (regs.itr.interval() == 0 || now ||
+ lastInterrupt + itr_interval <= curTick) {
if (interEvent.scheduled()) {
deschedule(interEvent);
}
cpuPostInt();
} else {
- Tick int_time = lastInterrupt + itr_interval;
- assert(int_time > 0);
- DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for tick %d\n",
+ Tick int_time = lastInterrupt + itr_interval;
+ assert(int_time > 0);
+ DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for tick %d\n",
int_time);
- if (!interEvent.scheduled()) {
- schedule(interEvent, int_time);
- }
+ if (!interEvent.scheduled()) {
+ schedule(interEvent, int_time);
+ }
}
}
@@ -759,7 +771,8 @@
{
if (regs.icr.int_assert()) {
regs.icr.int_assert(0);
- DPRINTF(EthernetIntr, "EINT: Clearing interrupt to CPU now. Vector
%#x\n",
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