changeset 83693f4b79fd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=83693f4b79fd
description:
inorder-alpha-port: initial inorder support of ALPHA
Edit AlphaISA to support the inorder model. Mostly alternate
constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard
to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit
resource. Give CPU accessor functions for access and also bind at construction
time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
diffstat:
16 files changed, 232 insertions(+), 26 deletions(-)
src/arch/SConscript | 1
src/arch/alpha/floatregfile.hh | 56 ++++++++++++++++++++++++++++
src/arch/alpha/isa/mem.isa | 39 +++++++++++++++++++
src/arch/alpha/miscregfile.cc | 16 ++++++--
src/arch/alpha/miscregfile.hh | 23 +++++++++--
src/arch/mips/regfile/misc_regfile.hh | 2 -
src/cpu/inorder/cpu.cc | 37 +++++++++++++++++-
src/cpu/inorder/cpu.hh | 14 +++++--
src/cpu/inorder/inorder_dyn_inst.hh | 7 +++
src/cpu/inorder/resource_pool.cc | 15 +++++++
src/cpu/inorder/resource_pool.hh | 6 ++-
src/cpu/inorder/resources/cache_unit.cc | 2 -
src/cpu/inorder/resources/mult_div_unit.cc | 2 -
src/cpu/inorder/resources/tlb_unit.cc | 25 +++++++++++-
src/cpu/inorder/resources/tlb_unit.hh | 5 +-
src/cpu/inorder/thread_context.hh | 8 ++--
diffs (truncated from 615 to 300 lines):
diff -r 2bbb49ca07a8 -r 83693f4b79fd src/arch/SConscript
--- a/src/arch/SConscript Tue May 12 15:01:13 2009 -0400
+++ b/src/arch/SConscript Tue May 12 15:01:13 2009 -0400
@@ -51,6 +51,7 @@
locked_mem.hh
microcode_rom.hh
mmaped_ipr.hh
+ mt.hh
process.hh
predecoder.hh
regfile.hh
diff -r 2bbb49ca07a8 -r 83693f4b79fd src/arch/alpha/floatregfile.hh
--- a/src/arch/alpha/floatregfile.hh Tue May 12 15:01:13 2009 -0400
+++ b/src/arch/alpha/floatregfile.hh Tue May 12 15:01:13 2009 -0400
@@ -42,6 +42,13 @@
namespace AlphaISA {
+const int SingleWidth = 32;
+const int SingleBytes = SingleWidth / 4;
+const int DoubleWidth = 64;
+const int DoubleBytes = DoubleWidth / 4;
+const int QuadWidth = 128;
+const int QuadBytes = QuadWidth / 4;
+
class FloatRegFile
{
public:
@@ -54,6 +61,55 @@
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
+
+ FloatReg
+ readReg(int floatReg)
+ {
+ return d[floatReg];
+ }
+
+ FloatReg
+ readReg(int floatReg, int width)
+ {
+ return readReg(floatReg);
+ }
+
+ FloatRegBits
+ readRegBits(int floatReg)
+ {
+ return q[floatReg];
+ }
+
+ FloatRegBits
+ readRegBits(int floatReg, int width)
+ {
+ return readRegBits(floatReg);
+ }
+
+ void
+ setReg(int floatReg, const FloatReg &val)
+ {
+ d[floatReg] = val;
+ }
+
+ void
+ setReg(int floatReg, const FloatReg &val, int width)
+ {
+ setReg(floatReg, val);
+ }
+
+ void
+ setRegBits(int floatReg, const FloatRegBits &val)
+ {
+ q[floatReg] = val;
+ }
+
+ void
+ setRegBits(int floatReg, const FloatRegBits &val, int width)
+ {
+ setRegBits(floatReg, val);
+ }
+
};
} // namespace AlphaISA
diff -r 2bbb49ca07a8 -r 83693f4b79fd src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa Tue May 12 15:01:13 2009 -0400
+++ b/src/arch/alpha/isa/mem.isa Tue May 12 15:01:13 2009 -0400
@@ -65,6 +65,8 @@
const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
const StaticInstPtr &memAccInst() const { return memAccPtr; }
+
+ Request::Flags memAccFlags() { return memAccessFlags; }
};
/**
@@ -176,6 +178,8 @@
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
+
+ %(MemAccSizeDeclare)s
};
}};
@@ -190,6 +194,25 @@
Trace::InstRecord *) const;
}};
+def template MemAccSizeDeclare {{
+ int memAccSize(%(CPU_exec_context)s *xc);
+}};
+
+def template MiscMemAccSize {{
+ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+ {
+ panic("Misc instruction does not support split access method!");
+ return 0;
+ }
+}};
+
+def template LoadStoreMemAccSize {{
+ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+ {
+ // Return the memory access size in bytes
+ return (%(mem_acc_size)d / 8);
+ }
+}};
def template EACompConstructor {{
/** TODO: change op_class to AddrGenOp or something (requires
@@ -620,6 +643,14 @@
}
}};
+def template MiscMemAccSize {{
+ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+ {
+ panic("Misc instruction does not support split access method!");
+ return 0;
+ }
+}};
+
// load instructions use Ra as dest, so check for
// Ra == 31 to detect nops
def template LoadNopCheckDecode {{
@@ -693,6 +724,11 @@
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
+ if (exec_template_base == 'Load' or exec_template_base == 'Store'):
+ memAccSizeTemplate = eval('LoadStoreMemAccSize')
+ else:
+ memAccSizeTemplate = eval('MiscMemAccSize')
+
# (header_output, decoder_output, decode_block, exec_output)
return (LoadStoreDeclare.subst(iop),
EACompConstructor.subst(ea_iop)
@@ -703,7 +739,8 @@
+ memAccExecTemplate.subst(memacc_iop)
+ fullExecTemplate.subst(iop)
+ initiateAccTemplate.subst(iop)
- + completeAccTemplate.subst(iop))
+ + completeAccTemplate.subst(iop)
+ + memAccSizeTemplate.subst(memacc_iop))
}};
def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
diff -r 2bbb49ca07a8 -r 83693f4b79fd src/arch/alpha/miscregfile.cc
--- a/src/arch/alpha/miscregfile.cc Tue May 12 15:01:13 2009 -0400
+++ b/src/arch/alpha/miscregfile.cc Tue May 12 15:01:13 2009 -0400
@@ -57,8 +57,15 @@
UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
}
+MiscRegFile::MiscRegFile(BaseCPU *_cpu)
+{
+ cpu = _cpu;
+ initializeIprTable();
+}
+
+
MiscReg
-MiscRegFile::readRegNoEffect(int misc_reg)
+MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -78,7 +85,7 @@
}
MiscReg
-MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
+MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid )
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -97,7 +104,7 @@
}
void
-MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val)
+MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -123,7 +130,8 @@
}
void
-MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
+ unsigned tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
diff -r 2bbb49ca07a8 -r 83693f4b79fd src/arch/alpha/miscregfile.hh
--- a/src/arch/alpha/miscregfile.hh Tue May 12 15:01:13 2009 -0400
+++ b/src/arch/alpha/miscregfile.hh Tue May 12 15:01:13 2009 -0400
@@ -41,6 +41,7 @@
class Checkpoint;
class ThreadContext;
+class BaseCPU;
namespace AlphaISA {
@@ -68,6 +69,8 @@
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
+ BaseCPU *cpu;
+
protected:
InternalProcReg readIpr(int idx, ThreadContext *tc);
void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
@@ -78,16 +81,18 @@
initializeIprTable();
}
+ MiscRegFile(BaseCPU *cpu);
+
// These functions should be removed once the simplescalar cpu
// model has been replaced.
int getInstAsid();
int getDataAsid();
- MiscReg readRegNoEffect(int misc_reg);
- MiscReg readReg(int misc_reg, ThreadContext *tc);
+ MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
+ MiscReg readReg(int misc_reg, ThreadContext *tc, unsigned tid = 0);
- void setRegNoEffect(int misc_reg, const MiscReg &val);
- void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+ void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
+ void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, unsigned
tid = 0);
void
clear()
@@ -101,6 +106,16 @@
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
+
+ void reset(std::string core_name, unsigned num_threads,
+ unsigned num_vpes, BaseCPU *_cpu)
+ { }
+
+
+ void expandForMultithreading(unsigned num_threads, unsigned num_vpes)
+ { }
+
+
};
void copyIprs(ThreadContext *src, ThreadContext *dest);
diff -r 2bbb49ca07a8 -r 83693f4b79fd src/arch/mips/regfile/misc_regfile.hh
--- a/src/arch/mips/regfile/misc_regfile.hh Tue May 12 15:01:13 2009 -0400
+++ b/src/arch/mips/regfile/misc_regfile.hh Tue May 12 15:01:13 2009 -0400
@@ -69,7 +69,7 @@
public:
MiscRegFile();
- MiscRegFile(BaseCPU *cpu);
+ MiscRegFile(BaseCPU *_cpu);
void init();
diff -r 2bbb49ca07a8 -r 83693f4b79fd src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Tue May 12 15:01:13 2009 -0400
+++ b/src/cpu/inorder/cpu.cc Tue May 12 15:01:13 2009 -0400
@@ -180,15 +180,26 @@
// Bind the fetch & data ports from the resource pool.
fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
if (fetchPortIdx == 0) {
- warn("Unable to find port to fetch instructions from.\n");
+ fatal("Unable to find port to fetch instructions from.\n");
}
dataPortIdx = resPool->getPortIdx(params->dataMemPort);
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