changeset a17798f2a52c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a17798f2a52c
description:
types: clean up types, especially signed vs unsigned
diffstat:
72 files changed, 329 insertions(+), 326 deletions(-)
src/arch/alpha/ev5.cc | 2 -
src/arch/alpha/interrupts.hh | 8 ++--
src/arch/alpha/isa/decoder.isa | 4 +-
src/arch/alpha/isa_traits.hh | 64 +++++++++++++++++-----------------
src/arch/alpha/process.cc | 7 +--
src/arch/alpha/stacktrace.hh | 8 ++--
src/base/atomicio.cc | 4 +-
src/base/chunk_generator.hh | 25 +++++++------
src/base/crc.cc | 37 +++++++------------
src/base/fast_alloc.hh | 2 -
src/base/loader/symtab.cc | 2 -
src/base/match.cc | 2 -
src/base/remote_gdb.cc | 8 ++--
src/base/sat_counter.cc | 2 -
src/base/sat_counter.hh | 6 ++-
src/base/statistics.cc | 2 -
src/base/statistics.hh | 2 -
src/base/timebuf.hh | 18 ++++-----
src/cpu/inorder/cpu.cc | 4 +-
src/cpu/inorder/cpu.hh | 2 -
src/cpu/inorder/pipeline_traits.hh | 2 -
src/cpu/memtest/memtest.cc | 2 -
src/cpu/ozone/cpu_impl.hh | 4 +-
src/cpu/pred/2bit_local.cc | 4 +-
src/cpu/pred/btb.cc | 4 +-
src/cpu/pred/ras.cc | 4 +-
src/cpu/simple/atomic.cc | 6 +--
src/cpu/simple/base.cc | 6 ++-
src/cpu/simple/timing.cc | 4 +-
src/dev/disk_image.cc | 4 +-
src/dev/disk_image.hh | 4 +-
src/dev/etherdump.hh | 2 -
src/dev/etherpkt.hh | 4 +-
src/dev/ethertap.hh | 4 +-
src/dev/i8254xGBe.cc | 40 +++++++++------------
src/dev/i8254xGBe.hh | 33 +++++++++--------
src/dev/i8254xGBe_defs.hh | 6 +--
src/dev/io_device.hh | 4 +-
src/dev/pktfifo.cc | 4 +-
src/dev/pktfifo.hh | 25 ++++++-------
src/dev/sinic.cc | 4 +-
src/dev/sinic.hh | 8 ++--
src/kern/linux/linux.cc | 2 -
src/mem/bus.cc | 10 ++---
src/mem/bus.hh | 8 ++--
src/mem/cache/base.cc | 4 +-
src/mem/cache/base.hh | 7 ++-
src/mem/cache/blk.hh | 4 +-
src/mem/cache/mshr.hh | 2 -
src/mem/cache/prefetch/base.hh | 2 -
src/mem/cache/tags/fa_lru.cc | 16 ++++----
src/mem/cache/tags/fa_lru.hh | 19 +++++-----
src/mem/cache/tags/iic.cc | 20 ++++------
src/mem/cache/tags/iic.hh | 51 ++++++++++++++-------------
src/mem/cache/tags/lru.cc | 19 ++++------
src/mem/cache/tags/lru.hh | 18 +++++----
src/mem/gems_common/ioutil/confio.cc | 4 +-
src/mem/packet.hh | 4 +-
src/mem/page_table.cc | 2 -
src/mem/physical.cc | 18 ++++-----
src/mem/physical.hh | 4 +-
src/mem/port.cc | 5 +-
src/mem/port.hh | 4 +-
src/mem/rubymem.cc | 2 -
src/sim/init.cc | 2 -
src/sim/process.cc | 4 +-
src/sim/process_impl.hh | 2 -
src/sim/pseudo_inst.cc | 2 -
src/sim/serialize.cc | 20 ++++------
src/sim/serialize.hh | 4 +-
src/sim/syscall_emul.hh | 7 +--
src/sim/system.hh | 2 -
diffs (truncated from 2233 to 300 lines):
diff -r f1076450ab2b -r a17798f2a52c src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Thu Jun 04 21:50:20 2009 -0700
+++ b/src/arch/alpha/ev5.cc Thu Jun 04 23:21:12 2009 -0700
@@ -351,7 +351,7 @@
case IPR_IPLR:
#ifdef DEBUG
- if (break_ipl != -1 && break_ipl == (val & 0x1f))
+ if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
debug_break();
#endif
diff -r f1076450ab2b -r a17798f2a52c src/arch/alpha/interrupts.hh
--- a/src/arch/alpha/interrupts.hh Thu Jun 04 21:50:20 2009 -0700
+++ b/src/arch/alpha/interrupts.hh Thu Jun 04 23:21:12 2009 -0700
@@ -139,14 +139,14 @@
Fault
getInterrupt(ThreadContext *tc)
{
- int ipl = 0;
- int summary = 0;
+ uint64_t ipl = 0;
+ uint64_t summary = 0;
if (tc->readMiscRegNoEffect(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
if (tc->readMiscRegNoEffect(IPR_SIRR)) {
- for (int i = INTLEVEL_SOFTWARE_MIN;
+ for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
i < INTLEVEL_SOFTWARE_MAX; i++) {
if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
// See table 4-19 of 21164 hardware reference
@@ -158,7 +158,7 @@
uint64_t interrupts = intstatus;
if (interrupts) {
- for (int i = INTLEVEL_EXTERNAL_MIN;
+ for (uint64_t i = INTLEVEL_EXTERNAL_MIN;
i < INTLEVEL_EXTERNAL_MAX; i++) {
if (interrupts & (ULL(1) << i)) {
// See table 4-19 of 21164 hardware reference
diff -r f1076450ab2b -r a17798f2a52c src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Thu Jun 04 21:50:20 2009 -0700
+++ b/src/arch/alpha/isa/decoder.isa Thu Jun 04 23:21:12 2009 -0700
@@ -114,7 +114,7 @@
0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
0x40: addlv({{
- uint32_t tmp = Ra.sl + Rb_or_imm.sl;
+ int32_t tmp = Ra.sl + Rb_or_imm.sl;
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
@@ -138,7 +138,7 @@
0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
0x49: sublv({{
- uint32_t tmp = Ra.sl - Rb_or_imm.sl;
+ int32_t tmp = Ra.sl - Rb_or_imm.sl;
// signed overflow detection is same as for add,
// except we need to look at the *complemented*
// sign bit of the subtrahend (Rb), i.e., if the initial
diff -r f1076450ab2b -r a17798f2a52c src/arch/alpha/isa_traits.hh
--- a/src/arch/alpha/isa_traits.hh Thu Jun 04 21:50:20 2009 -0700
+++ b/src/arch/alpha/isa_traits.hh Thu Jun 04 23:21:12 2009 -0700
@@ -127,45 +127,47 @@
// Constants Related to the number of registers
-const int NumIntArchRegs = 32;
-const int NumPALShadowRegs = 8;
-const int NumFloatArchRegs = 32;
-// @todo: Figure out what this number really should be.
-const int NumMiscArchRegs = 77;
+enum {
+ NumIntArchRegs = 32,
+ NumPALShadowRegs = 8,
+ NumFloatArchRegs = 32,
+ // @todo: Figure out what this number really should be.
+ NumMiscArchRegs = 77,
-const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
-const int NumFloatRegs = NumFloatArchRegs;
-const int NumMiscRegs = NumMiscArchRegs;
+ NumIntRegs = NumIntArchRegs + NumPALShadowRegs,
+ NumFloatRegs = NumFloatArchRegs,
+ NumMiscRegs = NumMiscArchRegs,
-const int TotalNumRegs =
- NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
+ TotalNumRegs =
+ NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs,
-const int TotalDataRegs = NumIntRegs + NumFloatRegs;
+ TotalDataRegs = NumIntRegs + NumFloatRegs,
-// semantically meaningful register indices
-const int ZeroReg = 31; // architecturally meaningful
-// the rest of these depend on the ABI
-const int StackPointerReg = 30;
-const int GlobalPointerReg = 29;
-const int ProcedureValueReg = 27;
-const int ReturnAddressReg = 26;
-const int ReturnValueReg = 0;
-const int FramePointerReg = 15;
+ // semantically meaningful register indices
+ ZeroReg = 31, // architecturally meaningful
+ // the rest of these depend on the ABI
+ StackPointerReg = 30,
+ GlobalPointerReg = 29,
+ ProcedureValueReg = 27,
+ ReturnAddressReg = 26,
+ ReturnValueReg = 0,
+ FramePointerReg = 15,
-const int SyscallNumReg = 0;
-const int FirstArgumentReg = 16;
-const int SyscallPseudoReturnReg = 20;
-const int SyscallSuccessReg = 19;
+ SyscallNumReg = 0,
+ FirstArgumentReg = 16,
+ SyscallPseudoReturnReg = 20,
+ SyscallSuccessReg = 19,
-const int LogVMPageSize = 13; // 8K bytes
-const int VMPageSize = (1 << LogVMPageSize);
+ LogVMPageSize = 13, // 8K bytes
+ VMPageSize = (1 << LogVMPageSize),
-const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+ BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
-const int MachineBytes = 8;
-const int WordBytes = 4;
-const int HalfwordBytes = 2;
-const int ByteBytes = 1;
+ MachineBytes = 8,
+ WordBytes = 4,
+ HalfwordBytes = 2,
+ ByteBytes = 1,
+};
// return a no-op instruction... used for instruction fetch faults
// Alpha UNOP (ldq_u r31,0(r0))
diff -r f1076450ab2b -r a17798f2a52c src/arch/alpha/process.cc
--- a/src/arch/alpha/process.cc Thu Jun 04 21:50:20 2009 -0700
+++ b/src/arch/alpha/process.cc Thu Jun 04 23:21:12 2009 -0700
@@ -100,11 +100,11 @@
int auxv_array_size = intSize * 2 * (auxv.size() + 1);
int arg_data_size = 0;
- for (int i = 0; i < argv.size(); ++i) {
+ for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
arg_data_size += argv[i].size() + 1;
}
int env_data_size = 0;
- for (int i = 0; i < envp.size(); ++i) {
+ for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
env_data_size += envp[i].size() + 1;
}
@@ -148,8 +148,7 @@
copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
//Copy the aux stuff
- for(int x = 0; x < auxv.size(); x++)
- {
+ for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
(uint8_t*)&(auxv[x].a_type), intSize);
initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
diff -r f1076450ab2b -r a17798f2a52c src/arch/alpha/stacktrace.hh
--- a/src/arch/alpha/stacktrace.hh Thu Jun 04 21:50:20 2009 -0700
+++ b/src/arch/alpha/stacktrace.hh Thu Jun 04 23:21:12 2009 -0700
@@ -91,9 +91,11 @@
public:
const std::vector<Addr> &getstack() const { return stack; }
- static const int user = 1;
- static const int console = 2;
- static const int unknown = 3;
+ enum {
+ user = 1,
+ console = 2,
+ unknown = 3
+ };
#if TRACING_ON
private:
diff -r f1076450ab2b -r a17798f2a52c src/base/atomicio.cc
--- a/src/base/atomicio.cc Thu Jun 04 21:50:20 2009 -0700
+++ b/src/base/atomicio.cc Thu Jun 04 23:21:12 2009 -0700
@@ -37,7 +37,7 @@
atomic_read(int fd, void *s, size_t n)
{
char *p = reinterpret_cast<char *>(s);
- ssize_t pos = 0;
+ size_t pos = 0;
// Keep reading until we've gotten all of the data.
while (n > pos) {
@@ -66,7 +66,7 @@
atomic_write(int fd, const void *s, size_t n)
{
const char *p = reinterpret_cast<const char *>(s);
- ssize_t pos = 0;
+ size_t pos = 0;
// Keep writing until we've written all of the data
while (n > pos) {
diff -r f1076450ab2b -r a17798f2a52c src/base/chunk_generator.hh
--- a/src/base/chunk_generator.hh Thu Jun 04 21:50:20 2009 -0700
+++ b/src/base/chunk_generator.hh Thu Jun 04 23:21:12 2009 -0700
@@ -37,8 +37,9 @@
*/
#include <algorithm>
+
#include "base/intmath.hh"
-#include "arch/isa_traits.hh" // for Addr
+#include "base/types.hh"
/**
* This class takes an arbitrary memory region (address/length pair)
@@ -61,13 +62,13 @@
/** The starting address of the next chunk (after the current one). */
Addr nextAddr;
/** The size of the current chunk (in bytes). */
- int curSize;
+ unsigned curSize;
/** The number of bytes remaining in the region after the current chunk. */
- int sizeLeft;
+ unsigned sizeLeft;
/** The start address so we can calculate offset in writing block. */
const Addr startAddr;
/** The maximum chunk size, e.g., the cache block size or page size. */
- const int chunkSize;
+ const unsigned chunkSize;
public:
/**
@@ -77,7 +78,7 @@
* @param _chunkSize The size/alignment of chunks into which
* the region should be decomposed.
*/
- ChunkGenerator(Addr _startAddr, int totalSize, int _chunkSize)
+ ChunkGenerator(Addr _startAddr, unsigned totalSize, unsigned _chunkSize)
: startAddr(_startAddr), chunkSize(_chunkSize)
{
// chunkSize must be a power of two
@@ -102,31 +103,33 @@
}
// how many bytes are left between curAddr and the end of this chunk?
- int left_in_chunk = nextAddr - curAddr;
+ unsigned left_in_chunk = nextAddr - curAddr;
curSize = std::min(totalSize, left_in_chunk);
sizeLeft = totalSize - curSize;
}
/** Return starting address of current chunk. */
- Addr addr() { return curAddr; }
+ Addr addr() const { return curAddr; }
/** Return size in bytes of current chunk. */
- int size() { return curSize; }
+ unsigned size() const { return curSize; }
/** Number of bytes we have already chunked up. */
- int complete() { return curAddr - startAddr; }
+ unsigned complete() const { return curAddr - startAddr; }
+
/**
* Are we done? That is, did the last call to next() advance
* past the end of the region?
* @return True if yes, false if more to go.
*/
- bool done() { return (curSize == 0); }
+ bool done() const { return (curSize == 0); }
/**
* Advance generator to next chunk.
* @return True if successful, false if unsuccessful
* (because we were at the last chunk).
*/
- bool next()
+ bool
+ next()
{
if (sizeLeft == 0) {
curSize = 0;
diff -r f1076450ab2b -r a17798f2a52c src/base/crc.cc
--- a/src/base/crc.cc Thu Jun 04 21:50:20 2009 -0700
+++ b/src/base/crc.cc Thu Jun 04 23:21:12 2009 -0700
@@ -48,15 +48,12 @@
uint32_t
crc32le(const uint8_t *buf, size_t len)
{
- uint32_t c, crc, carry;
- size_t i, j;
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