changeset 2f66c82a2e20 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=2f66c82a2e20 description: ARM: Add a hello world regression.
diffstat: 4 files changed, 149 insertions(+) tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini | 91 +++++++++++ tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr | 5 tests/quick/00.hello/ref/arm/linux/simple-atomic/simout | 17 ++ tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt | 36 ++++ diffs (165 lines): diff -r ee66c4856854 -r 2f66c82a2e20 tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini Tue Jun 09 23:55:53 2009 -0700 @@ -0,0 +1,91 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +UnifiedTLB=true +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff -r ee66c4856854 -r 2f66c82a2e20 tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr Tue Jun 09 23:55:53 2009 -0700 @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: allowing mmap of file @ fd 4294967295. This will break if not /dev/zero. +For more information see: http://www.m5sim.org/warn/3a2134f6 +hack: be nice to actually delete the event here diff -r ee66c4856854 -r 2f66c82a2e20 tests/quick/00.hello/ref/arm/linux/simple-atomic/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout Tue Jun 09 23:55:53 2009 -0700 @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jun 9 2009 23:46:33 +M5 revision 6639f3c716a6 6238 default qtip tip armreg.patch qbase +M5 started Jun 9 2009 23:53:49 +M5 executing on fajita +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 2299000 because target called exit() diff -r ee66c4856854 -r 2f66c82a2e20 tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt Tue Jun 09 23:55:53 2009 -0700 @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 79163 # Simulator instruction rate (inst/s) +host_mem_usage 189980 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 39442081 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 4598 # Number of instructions simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 2299000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 4599 # number of cpu cycles simulated +system.cpu.num_insts 4598 # Number of instructions executed +system.cpu.num_refs 1851 # Number of memory references +system.cpu.workload.PROG:num_syscalls 14 # Number of system calls + +---------- End Simulation Statistics ---------- _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
