changeset 3a1698fbbc9f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3a1698fbbc9f
description:
ARM: Make the isa parser aware that CPSR is being used.
diffstat:
7 files changed, 80 insertions(+), 45 deletions(-)
src/arch/arm/isa/decoder.isa | 3 --
src/arch/arm/isa/formats/branch.isa | 4 +--
src/arch/arm/isa/formats/fp.isa | 31 +++++++++++++++++---------
src/arch/arm/isa/formats/macromem.isa | 10 ++++++--
src/arch/arm/isa/formats/mem.isa | 24 ++++++++++----------
src/arch/arm/isa/formats/pred.isa | 39 ++++++++++++++++++++++-----------
src/arch/arm/isa/formats/util.isa | 14 +++++++----
diffs (truncated from 363 to 300 lines):
diff -r 1cee707c1228 -r 3a1698fbbc9f src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Sun Jun 21 09:21:07 2009 -0700
+++ b/src/arch/arm/isa/decoder.isa Sun Jun 21 09:37:41 2009 -0700
@@ -830,8 +830,7 @@
}
format PredOp {
// ARM System Call (SoftWare Interrupt)
- 1: swi({{ if
(testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR),
- condCode))
+ 1: swi({{ if (testPredicate(Cpsr, condCode))
{
//xc->syscall(R7);
xc->syscall(IMMED_23_0);
diff -r 1cee707c1228 -r 3a1698fbbc9f src/arch/arm/isa/formats/branch.isa
--- a/src/arch/arm/isa/formats/branch.isa Sun Jun 21 09:21:07 2009 -0700
+++ b/src/arch/arm/isa/formats/branch.isa Sun Jun 21 09:37:41 2009 -0700
@@ -234,7 +234,7 @@
else:
inst_flags += ('IsCondControl', )
- icode = 'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR),
condCode)) {\n'
+ icode = 'if (testPredicate(Cpsr, condCode)) {\n'
icode += code
icode += ' NPC = NPC + 4 + disp;\n'
icode += '} else {\n'
@@ -268,7 +268,7 @@
#Condition code
- icode = 'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR),
condCode)) {\n'
+ icode = 'if (testPredicate(Cpsr, condCode)) {\n'
icode += code
icode += ' NPC = Rm & 0xfffffffe; // Masks off bottom bit\n'
icode += '} else {\n'
diff -r 1cee707c1228 -r 3a1698fbbc9f src/arch/arm/isa/formats/fp.isa
--- a/src/arch/arm/isa/formats/fp.isa Sun Jun 21 09:21:07 2009 -0700
+++ b/src/arch/arm/isa/formats/fp.isa Sun Jun 21 09:37:41 2009 -0700
@@ -65,12 +65,11 @@
%(op_decl)s;
%(op_rd)s;
- %(code)s;
-
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR),
condCode) &&
- fault == NoFault)
- {
- %(op_wb)s;
+ if (%(predicate_test)s) {
+ %(code)s;
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
}
return fault;
@@ -102,13 +101,19 @@
orig_code = code
cblk = code
- iop = InstObjParams(name, Name, 'FPAOp', cblk, flags)
+ iop = InstObjParams(name, Name, 'FPAOp',
+ {"code": cblk,
+ "predicate_test": predicateTest},
+ flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = FPAExecute.subst(iop)
sng_cblk = code
- sng_iop = InstObjParams(name, Name+'S', 'FPAOp', sng_cblk, flags)
+ sng_iop = InstObjParams(name, Name+'S', 'FPAOp',
+ {"code": sng_cblk,
+ "predicate_test": predicateTest},
+ flags)
header_output += BasicDeclare.subst(sng_iop)
decoder_output += BasicConstructor.subst(sng_iop)
exec_output += FPAExecute.subst(sng_iop)
@@ -116,7 +121,10 @@
dbl_code = re.sub(r'\.sf', '.df', orig_code)
dbl_cblk = dbl_code
- dbl_iop = InstObjParams(name, Name+'D', 'FPAOp', dbl_cblk, flags)
+ dbl_iop = InstObjParams(name, Name+'D', 'FPAOp',
+ {"code": dbl_cblk,
+ "predicate_test": predicateTest},
+ flags)
header_output += BasicDeclare.subst(dbl_iop)
decoder_output += BasicConstructor.subst(dbl_iop)
exec_output += FPAExecute.subst(dbl_iop)
@@ -140,7 +148,10 @@
def format FloatCmp(fReg1, fReg2, *flags) {{
code = calcFPCcCode % vars()
- iop = InstObjParams(name, Name, 'FPAOp', code, flags)
+ iop = InstObjParams(name, Name, 'FPAOp',
+ {"code": code,
+ "predicate_test": predicateTest},
+ flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff -r 1cee707c1228 -r 3a1698fbbc9f src/arch/arm/isa/formats/macromem.isa
--- a/src/arch/arm/isa/formats/macromem.isa Sun Jun 21 09:21:07 2009 -0700
+++ b/src/arch/arm/isa/formats/macromem.isa Sun Jun 21 09:37:41 2009 -0700
@@ -370,7 +370,10 @@
}};
def format ArmMacroFPAOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{
- iop = InstObjParams(name, Name, 'ArmMacroFPAOp', code, opt_flags)
+ iop = InstObjParams(name, Name, 'ArmMacroFPAOp',
+ {"code": code,
+ "predicate_test": predicateTest},
+ opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = MacroFPAConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -378,7 +381,10 @@
}};
def format ArmMacroFMOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{
- iop = InstObjParams(name, Name, 'ArmMacroFMOp', code, opt_flags)
+ iop = InstObjParams(name, Name, 'ArmMacroFMOp',
+ {"code": code,
+ "predicate_test": predicateTest},
+ opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = MacroFMConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff -r 1cee707c1228 -r 3a1698fbbc9f src/arch/arm/isa/formats/mem.isa
--- a/src/arch/arm/isa/formats/mem.isa Sun Jun 21 09:21:07 2009 -0700
+++ b/src/arch/arm/isa/formats/mem.isa Sun Jun 21 09:37:41 2009 -0700
@@ -216,7 +216,7 @@
%(op_rd)s;
%(ea_code)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
if (fault == NoFault) {
%(op_wb)s;
@@ -241,7 +241,7 @@
%(op_rd)s;
EA = xc->getEA();
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem,
memAccessFlags);
@@ -270,7 +270,7 @@
%(op_rd)s;
%(ea_code)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem,
memAccessFlags);
@@ -299,7 +299,7 @@
%(op_rd)s;
%(ea_code)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem,
memAccessFlags);
@@ -322,7 +322,7 @@
%(op_decl)s;
%(op_rd)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
// ARM instructions will not have a pkt if the predicate is false
Mem = pkt->get<typeof(Mem)>();
@@ -353,7 +353,7 @@
%(op_decl)s;
%(op_rd)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
EA = xc->getEA();
@@ -385,7 +385,7 @@
%(op_rd)s;
%(ea_code)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
if (fault == NoFault) {
%(memacc_code)s;
@@ -418,7 +418,7 @@
%(op_rd)s;
%(ea_code)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
if (fault == NoFault) {
%(memacc_code)s;
@@ -451,7 +451,7 @@
%(fp_enable_check)s;
%(op_dest_decl)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
if (fault == NoFault) {
%(op_wb)s;
@@ -472,7 +472,7 @@
%(fp_enable_check)s;
%(op_dest_decl)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
if (fault == NoFault) {
%(op_wb)s;
@@ -495,7 +495,7 @@
%(op_decl)s;
%(op_rd)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
EA = xc->getEA();
@@ -520,7 +520,7 @@
%(op_rd)s;
%(ea_code)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
if (fault == NoFault) {
%(memacc_code)s;
diff -r 1cee707c1228 -r 3a1698fbbc9f src/arch/arm/isa/formats/pred.isa
--- a/src/arch/arm/isa/formats/pred.isa Sun Jun 21 09:21:07 2009 -0700
+++ b/src/arch/arm/isa/formats/pred.isa Sun Jun 21 09:37:41 2009 -0700
@@ -161,26 +161,26 @@
}};
+let {{
+ predicateTest = 'testPredicate(Cpsr, condCode)'
+}};
+
def template PredOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord
*traceData) const
{
Fault fault = NoFault;
-
- %(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
- %(code)s;
- if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
+ if (%(predicate_test)s)
{
+ %(fp_enable_check)s;
+ %(code)s;
if (fault == NoFault)
{
%(op_wb)s;
}
}
- else
- return NoFault;
- // Predicated false instructions should not return faults
return fault;
}
@@ -281,7 +281,10 @@
}};
def format PredOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'PredOp', code, opt_flags)
+ iop = InstObjParams(name, Name, 'PredOp',
+ {"code": code,
+ "predicate_test": predicateTest},
+ opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -289,7 +292,10 @@
}};
def format PredImmOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'PredImmOp', code, opt_flags)
+ iop = InstObjParams(name, Name, 'PredImmOp',
+ {"code": code,
+ "predicate_test": predicateTest},
+ opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
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