changeset 8abc40611938 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8abc40611938
description:
ARM: Move util functions out of the isa desc.
diffstat:
5 files changed, 279 insertions(+), 290 deletions(-)
src/arch/arm/insts/static_inst.cc | 228 ++++++++++++++++++++++++++++++-
src/arch/arm/insts/static_inst.hh | 59 ++++++--
src/arch/arm/isa/main.isa | 3
src/arch/arm/isa/util.isa | 271 -------------------------------------
src/arch/arm/types.hh | 8 +
diffs (truncated from 623 to 300 lines):
diff -r 988a001820f8 -r 8abc40611938 src/arch/arm/insts/static_inst.cc
--- a/src/arch/arm/insts/static_inst.cc Sun Jun 21 17:21:25 2009 -0700
+++ b/src/arch/arm/insts/static_inst.cc Sun Jun 21 22:50:33 2009 -0700
@@ -31,7 +31,228 @@
namespace ArmISA
{
-void ArmStaticInst::printReg(std::ostream &os, int reg) const
+static int32_t arm_NEG(int32_t val) { return (val >> 31); }
+static int32_t arm_POS(int32_t val) { return ((~val) >> 31); }
+
+// Shift Rm by an immediate value
+int32_t
+ArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt,
+ uint32_t type, uint32_t cfval) const
+{
+ enum ArmShiftType shiftType;
+ shiftType = (enum ArmShiftType) type;
+
+ switch (shiftType)
+ {
+ case LSL:
+ return (base << shamt);
+ case LSR:
+ if (shamt == 0)
+ return (0);
+ else
+ return (base >> shamt);
+ case ASR:
+ if (shamt == 0)
+ return ((uint32_t) ((int32_t) base >> 31L));
+ else
+ return ((uint32_t) (((int32_t) base) >> shamt));
+ case ROR:
+ //shamt = shamt & 0x1f;
+ if (shamt == 0)
+ return (cfval << 31) | (base >> 1); // RRX
+ else
+ return (base << (32 - shamt)) | (base >> shamt);
+ default:
+ fprintf(stderr, "Unhandled shift type\n");
+ exit(1);
+ break;
+ }
+ return 0;
+}
+
+// Shift Rm by Rs
+int32_t
+ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt,
+ uint32_t type, uint32_t cfval) const
+{
+ enum ArmShiftType shiftType;
+ shiftType = (enum ArmShiftType) type;
+
+ switch (shiftType)
+ {
+ case LSL:
+ if (shamt == 0)
+ return (base);
+ else if (shamt >= 32)
+ return (0);
+ else
+ return (base << shamt);
+ case LSR:
+ if (shamt == 0)
+ return (base);
+ else if (shamt >= 32)
+ return (0);
+ else
+ return (base >> shamt);
+ case ASR:
+ if (shamt == 0)
+ return base;
+ else if (shamt >= 32)
+ return ((uint32_t) ((int32_t) base >> 31L));
+ else
+ return ((uint32_t) (((int32_t) base) >> (int) shamt));
+ case ROR:
+ shamt = shamt & 0x1f;
+ if (shamt == 0)
+ return (base);
+ else
+ return ((base << (32 - shamt)) | (base >> shamt));
+ default:
+ fprintf(stderr, "Unhandled shift type\n");
+ exit(1);
+ break;
+ }
+ return 0;
+}
+
+
+// Generate C for a shift by immediate
+int32_t
+ArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt,
+ uint32_t type, uint32_t cfval) const
+{
+ enum ArmShiftType shiftType;
+ shiftType = (enum ArmShiftType) type;
+
+ switch (shiftType)
+ {
+ case LSL:
+ return (base >> (32 - shamt)) & 1;
+ case LSR:
+ if (shamt == 0)
+ return (base >> 31) & 1;
+ else
+ return (base >> (shamt - 1)) & 1;
+ case ASR:
+ if (shamt == 0)
+ return (base >> 31L);
+ else
+ return ((uint32_t) (((int32_t) base) >> (shamt - 1))) & 1;
+ case ROR:
+ shamt = shamt & 0x1f;
+ if (shamt == 0)
+ return (base & 1); // RRX
+ else
+ return (base >> (shamt - 1)) & 1;
+ default:
+ fprintf(stderr, "Unhandled shift type\n");
+ exit(1);
+ break;
+
+ }
+ return 0;
+}
+
+
+// Generate C for a shift by Rs
+int32_t
+ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
+ uint32_t type, uint32_t cfval) const
+{
+ enum ArmShiftType shiftType;
+ shiftType = (enum ArmShiftType) type;
+
+ switch (shiftType)
+ {
+ case LSL:
+ if (shamt == 0)
+ return (!!cfval);
+ else if (shamt == 32)
+ return (base & 1);
+ else if (shamt > 32)
+ return (0);
+ else
+ return ((base >> (32 - shamt)) & 1);
+ case LSR:
+ if (shamt == 0)
+ return (!!cfval);
+ else if (shamt == 32)
+ return (base >> 31);
+ else if (shamt > 32)
+ return (0);
+ else
+ return ((base >> (shamt - 1)) & 1);
+ case ASR:
+ if (shamt == 0)
+ return (!!cfval);
+ else if (shamt >= 32)
+ return (base >> 31L);
+ else
+ return (((uint32_t) (((int32_t) base) >> (shamt - 1))) & 1);
+ case ROR:
+ if (shamt == 0)
+ return (!!cfval);
+ shamt = shamt & 0x1f;
+ if (shamt == 0)
+ return (base >> 31); // RRX
+ else
+ return ((base >> (shamt - 1)) & 1);
+ default:
+ fprintf(stderr, "Unhandled shift type\n");
+ exit(1);
+ break;
+
+ }
+ return 0;
+}
+
+
+// Generate the appropriate carry bit for an addition operation
+int32_t
+ArmStaticInst::arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const
+{
+ if ((lhs | rhs) >> 30)
+ return ((arm_NEG(lhs) && arm_NEG(rhs)) ||
+ (arm_NEG(lhs) && arm_POS(result)) ||
+ (arm_NEG(rhs) && arm_POS(result)));
+
+ return 0;
+}
+
+// Generate the appropriate carry bit for a subtraction operation
+int32_t
+ArmStaticInst::arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const
+{
+ if ((lhs >= rhs) || ((rhs | lhs) >> 31))
+ return ((arm_NEG(lhs) && arm_POS(rhs)) ||
+ (arm_NEG(lhs) && arm_POS(result)) ||
+ (arm_POS(rhs) && arm_POS(result)));
+
+ return 0;
+}
+
+int32_t
+ArmStaticInst::arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const
+{
+ if ((lhs | rhs) >> 30)
+ return ((arm_NEG(lhs) && arm_NEG(rhs) && arm_POS(result)) ||
+ (arm_POS(lhs) && arm_POS(rhs) && arm_NEG(result)));
+
+ return 0;
+}
+
+int32_t
+ArmStaticInst::arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const
+{
+ if ((lhs >= rhs) || ((rhs | lhs) >> 31))
+ return ((arm_NEG(lhs) && arm_POS(rhs) && arm_POS(result)) ||
+ (arm_POS(lhs) && arm_NEG(rhs) && arm_NEG(result)));
+
+ return 0;
+}
+
+void
+ArmStaticInst::printReg(std::ostream &os, int reg) const
{
if (reg < FP_Base_DepTag) {
ccprintf(os, "r%d", reg);
@@ -41,8 +262,9 @@
}
}
-std::string ArmStaticInst::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
+std::string
+ArmStaticInst::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
{
std::stringstream ss;
diff -r 988a001820f8 -r 8abc40611938 src/arch/arm/insts/static_inst.hh
--- a/src/arch/arm/insts/static_inst.hh Sun Jun 21 17:21:25 2009 -0700
+++ b/src/arch/arm/insts/static_inst.hh Sun Jun 21 22:50:33 2009 -0700
@@ -34,22 +34,55 @@
namespace ArmISA
{
- class ArmStaticInst : public StaticInst
+class ArmStaticInst : public StaticInst
+{
+ protected:
+ // Shift Rm by an immediate value
+ int32_t
+ shift_rm_imm(uint32_t base, uint32_t shamt,
+ uint32_t type, uint32_t cfval) const;
+
+ // Shift Rm by Rs
+ int32_t
+ shift_rm_rs(uint32_t base, uint32_t shamt,
+ uint32_t type, uint32_t cfval) const;
+
+ // Generate C for a shift by immediate
+ int32_t
+ shift_carry_imm(uint32_t base, uint32_t shamt,
+ uint32_t type, uint32_t cfval) const;
+
+ // Generate C for a shift by Rs
+ int32_t
+ shift_carry_rs(uint32_t base, uint32_t shamt,
+ uint32_t type, uint32_t cfval) const;
+
+ // Generate the appropriate carry bit for an addition operation
+ int32_t
+ arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const;
+
+ // Generate the appropriate carry bit for a subtraction operation
+ int32_t
+ arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const;
+
+ int32_t
+ arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
+
+ int32_t
+ arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
+
+ // Constructor
+ ArmStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : StaticInst(mnem, _machInst, __opClass)
{
- protected:
+ }
- // Constructor
- ArmStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
- : StaticInst(mnem, _machInst, __opClass)
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
