changeset 588457e03a81 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=588457e03a81
description:
ARM: Show more information when disassembling data processing
intstructions.
This will need more work, but it should be a lot closer.
diffstat:
4 files changed, 89 insertions(+), 58 deletions(-)
src/arch/arm/insts/pred_inst.cc | 55 -----------------------
src/arch/arm/insts/pred_inst.hh | 4 -
src/arch/arm/insts/static_inst.cc | 85 +++++++++++++++++++++++++++++++++++++
src/arch/arm/insts/static_inst.hh | 3 +
diffs (196 lines):
diff -r 981fc6fba01a -r 588457e03a81 src/arch/arm/insts/pred_inst.cc
--- a/src/arch/arm/insts/pred_inst.cc Sat Jun 27 00:29:30 2009 -0700
+++ b/src/arch/arm/insts/pred_inst.cc Sat Jun 27 00:30:23 2009 -0700
@@ -35,60 +35,7 @@
PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
- printMnemonic(ss);
- if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
- }
-
- ss << ", ";
-
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- ss << ", ";
- }
-
- return ss.str();
-}
-
-std::string
-PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
- std::stringstream ss;
-
- ccprintf(ss, "%-10s ", mnemonic);
-
- if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
- }
-
- ss << ", ";
-
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- ss << ", ";
- }
-
- return ss.str();
-}
-
-std::string
-PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
- std::stringstream ss;
-
- ccprintf(ss, "%-10s ", mnemonic);
-
- if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
- }
-
- ss << ", ";
-
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- ss << ", ";
- }
-
+ printDataInst(ss);
return ss.str();
}
diff -r 981fc6fba01a -r 588457e03a81 src/arch/arm/insts/pred_inst.hh
--- a/src/arch/arm/insts/pred_inst.hh Sat Jun 27 00:29:30 2009 -0700
+++ b/src/arch/arm/insts/pred_inst.hh Sat Jun 27 00:30:23 2009 -0700
@@ -82,8 +82,6 @@
if (rotate != 0)
rotated_carry = (rotated_imm >> 31) & 1;
}
-
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
};
/**
@@ -102,8 +100,6 @@
shift_size(machInst.shiftSize), shift(machInst.shift)
{
}
-
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
};
/**
diff -r 981fc6fba01a -r 588457e03a81 src/arch/arm/insts/static_inst.cc
--- a/src/arch/arm/insts/static_inst.cc Sat Jun 27 00:29:30 2009 -0700
+++ b/src/arch/arm/insts/static_inst.cc Sat Jun 27 00:30:23 2009 -0700
@@ -327,6 +327,91 @@
}
}
+void
+ArmStaticInst::printShiftOperand(std::ostream &os) const
+{
+ // Shifter operand
+ if (bits((uint32_t)machInst, 25)) {
+ // Immediate form
+ unsigned rotate = machInst.rotate * 2;
+ uint32_t imm = machInst.imm;
+ ccprintf(os, "#%#x", (imm << (32 - rotate)) | (imm >> rotate));
+ } else {
+ // Register form
+ printReg(os, machInst.rm);
+
+ bool immShift = (machInst.opcode4 == 0);
+ bool done = false;
+ unsigned shiftAmt = (machInst.shiftSize);
+ ArmShiftType type = (ArmShiftType)(uint32_t)machInst.shift;
+
+ if ((type == LSR || type == ASR) && immShift && shiftAmt == 0)
+ shiftAmt = 32;
+
+ switch (type) {
+ case LSL:
+ if (immShift && shiftAmt == 0) {
+ done = true;
+ break;
+ }
+ os << ", LSL";
+ break;
+ case LSR:
+ os << ", LSR";
+ break;
+ case ASR:
+ os << ", ASR";
+ break;
+ case ROR:
+ if (immShift && shiftAmt == 0) {
+ os << ", RRX";
+ done = true;
+ break;
+ }
+ os << ", ROR";
+ break;
+ default:
+ panic("Tried to disassemble unrecognized shift type.\n");
+ }
+ if (!done) {
+ os << " ";
+ if (immShift)
+ os << "#" << shiftAmt;
+ else
+ printReg(os, machInst.rs);
+ }
+ }
+}
+
+void
+ArmStaticInst::printDataInst(std::ostream &os) const
+{
+ printMnemonic(os, machInst.sField ? "s" : "");
+ //XXX It would be nice if the decoder figured this all out for us.
+ unsigned opcode = machInst.opcode24_21;
+ bool firstOp = true;
+
+ // Destination
+ // Cmp, cmn, teq, and tst don't have one.
+ if (opcode < 8 || opcode > 0xb) {
+ firstOp = false;
+ printReg(os, machInst.rd);
+ }
+
+ // Source 1.
+ // Mov and Movn don't have one of these.
+ if (opcode != 0xd && opcode != 0xf) {
+ if (!firstOp)
+ os << ", ";
+ firstOp = false;
+ printReg(os, machInst.rn);
+ }
+
+ if (!firstOp)
+ os << ", ";
+ printShiftOperand(os);
+}
+
std::string
ArmStaticInst::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
diff -r 981fc6fba01a -r 588457e03a81 src/arch/arm/insts/static_inst.hh
--- a/src/arch/arm/insts/static_inst.hh Sat Jun 27 00:29:30 2009 -0700
+++ b/src/arch/arm/insts/static_inst.hh Sat Jun 27 00:30:23 2009 -0700
@@ -68,8 +68,11 @@
void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
const std::string &prefix, const Addr addr,
const std::string &suffix) const;
+ void printShiftOperand(std::ostream &os) const;
+ void printDataInst(std::ostream &os) const;
+
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
