changeset eae881827513 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=eae881827513
description:
inorder: Fix up some reference stats.
diffstat:
6 files changed, 112 insertions(+), 112 deletions(-)
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini | 2
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout | 8
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 106 +++++-----
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini | 2
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout | 8
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 98 ++++-----
diffs (truncated from 574 to 300 lines):
diff -r 20167772fb15 -r eae881827513
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini Thu Jul
02 23:23:06 2009 -0700
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini Sat Jul
04 21:46:23 2009 -0700
@@ -190,7 +190,7 @@
env=
errout=cerr
euid=100
-executable=/n/poolfs/z/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
diff -r 20167772fb15 -r eae881827513
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout Thu Jul
02 23:23:06 2009 -0700
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout Sat Jul
04 21:46:23 2009 -0700
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled May 12 2009 12:20:30
-M5 revision 2eebd457f8fc 6197 default qtip tip inorder-vortex-regress
-M5 started May 12 2009 12:20:31
-M5 executing on zooks
+M5 compiled Jul 4 2009 20:43:52
+M5 revision 20167772fb15 6281 default tip
+M5 started Jul 4 2009 20:43:52
+M5 executing on tater
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re
tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff -r 20167772fb15 -r eae881827513
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt Thu Jul
02 23:23:06 2009 -0700
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt Sat Jul
04 21:46:23 2009 -0700
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 51305 #
Simulator instruction rate (inst/s)
-host_mem_usage 216648 #
Number of bytes of host memory used
-host_seconds 1721.87 #
Real time elapsed on the host
-host_tick_rate 63437429 #
Simulator tick rate (ticks/s)
+host_inst_rate 66323 #
Simulator instruction rate (inst/s)
+host_mem_usage 296324 #
Number of bytes of host memory used
+host_seconds 1331.98 #
Real time elapsed on the host
+host_tick_rate 81990812 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 88340673 #
Number of instructions simulated
-sim_seconds 0.109231 #
Number of seconds simulated
-sim_ticks 109230836500 #
Number of ticks simulated
+sim_seconds 0.109210 #
Number of seconds simulated
+sim_ticks 109210014500 #
Number of ticks simulated
system.cpu.AGEN-Unit.instReqsProcessed 35224018 #
Number of Instructions Requests that completed in this resource.
system.cpu.Branch-Predictor.instReqsProcessed 88340674
# Number of Instructions Requests that completed in this resource.
system.cpu.Branch-Predictor.predictedNotTaken 10443271
# Number of Branches Predicted As Not Taken (False).
@@ -28,27 +28,27 @@
system.cpu.RegFile-Manager.instReqsProcessed 158796488
# Number of Instructions Requests that completed in this resource.
system.cpu.committedInsts 88340673 #
Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 88340673 #
Number of Instructions Simulated (Total)
-system.cpu.cpi 2.472946 #
CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 2.472946 #
CPI: Total CPI of All Threads
+system.cpu.cpi 2.472474 #
CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 2.472474 #
CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 20276638 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 38182.186102
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35069.874601
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 38181.240129
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35069.166968
# average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215854 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2320866000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 2320808500 #
number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002998 #
miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60784 #
number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 18 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2131056000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2131013000
# number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 #
mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60766 #
number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56050.509703
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53050.509703
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56049.825426
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53049.825426
# average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14463584 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 8395974000 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 8395871500 #
number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010250 #
miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 149793 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 7946595000
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 7946492500
# number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 #
mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 149793 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
@@ -60,29 +60,29 @@
system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50892.737573 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47861.411766
# average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 50891.977756 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 47860.720748
# average overall mshr miss latency
system.cpu.dcache.demand_hits 34679438 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10716840000 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 10716680000 #
number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.006035 #
miss rate for demand accesses
system.cpu.dcache.demand_misses 210577 #
number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 18 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10077651000
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 10077505500
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006035 #
mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 210559 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 34890015 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 50892.737573
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 47861.411766
# average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 50891.977756
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 47860.720748
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 34679438 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 10716840000 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 10716680000 #
number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.006035 #
miss rate for overall accesses
system.cpu.dcache.overall_misses 210577 #
number of overall misses
system.cpu.dcache.overall_mshr_hits 18 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10077651000
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 10077505500
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006035 #
mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 210559 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
@@ -90,7 +90,7 @@
system.cpu.dcache.replacements 200248 #
number of replacements
system.cpu.dcache.sampled_refs 204344 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4077.186045 #
Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4077.182458 #
Cycle average of tags in use
system.cpu.dcache.total_refs 34685659 #
Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 848449000 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147714 #
number of writebacks
@@ -112,14 +112,14 @@
system.cpu.dtb.write_hits 14613377 #
DTB write hits
system.cpu.dtb.write_misses 7252 #
DTB write misses
system.cpu.icache.ReadReq_accesses 96166938 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 19084.255120
# average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15849.213376
# average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 19084.949617
# average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15849.033723
# average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 96087744 #
number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1511358500 #
number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 1511413500 #
number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000824 #
miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 79194 #
number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1266 #
number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 1235097500
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 1235083500
# number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000810 #
mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 77928 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
@@ -131,29 +131,29 @@
system.cpu.icache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
system.cpu.icache.demand_accesses 96166938 #
number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 19084.255120 #
average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15849.213376
# average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 19084.949617 #
average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15849.033723
# average overall mshr miss latency
system.cpu.icache.demand_hits 96087744 #
number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1511358500 #
number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 1511413500 #
number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000824 #
miss rate for demand accesses
system.cpu.icache.demand_misses 79194 #
number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1266 #
number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1235097500
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 1235083500
# number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000810 #
mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 77928 #
number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.cpu.icache.overall_accesses 96166938 #
number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 19084.255120
# average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15849.213376
# average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 19084.949617
# average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15849.033723
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
system.cpu.icache.overall_hits 96087744 #
number of overall hits
-system.cpu.icache.overall_miss_latency 1511358500 #
number of overall miss cycles
+system.cpu.icache.overall_miss_latency 1511413500 #
number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000824 #
miss rate for overall accesses
system.cpu.icache.overall_misses 79194 #
number of overall misses
system.cpu.icache.overall_mshr_hits 1266 #
number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1235097500
# number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 1235083500
# number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000810 #
mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 77928 #
number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
@@ -161,13 +161,13 @@
system.cpu.icache.replacements 75882 #
number of replacements
system.cpu.icache.sampled_refs 77928 #
Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1874.324882 #
Cycle average of tags in use
+system.cpu.icache.tagsinuse 1874.320715 #
Cycle average of tags in use
system.cpu.icache.total_refs 96087744 #
Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 #
number of writebacks
system.cpu.icache_port.instReqsProcessed 96166940 #
Number of Instructions Requests that completed in this resource.
-system.cpu.ipc 0.404376 #
IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.404376 #
IPC: Total IPC of All Threads
+system.cpu.ipc 0.404453 #
IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.404453 #
IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 #
DTB accesses
system.cpu.itb.data_acv 0 #
DTB access violations
system.cpu.itb.data_hits 0 #
DTB hits
@@ -185,28 +185,28 @@
system.cpu.itb.write_hits 0 #
DTB write hits
system.cpu.itb.write_misses 0 #
DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143578 #
number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52039.532519
# average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52038.849963
# average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.083578
# average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 7471732000 #
number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 7471634000 #
number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 #
miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 143578 #
number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743132000
# number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1
# mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 143578 #
number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 138694 #
number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52317.460317
# average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52316.057051
# average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40003.485162
# average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 95224 #
number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 2274240000 #
number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 2274179000 #
number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.313424 #
miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 43470 #
number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1738951500
# number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313424 #
mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 43470 #
number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 6215 #
number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51994.529364
# average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51993.805310
# average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000.884956
# average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 323146000
# number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 323141500
# number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 #
miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 6215 #
number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248605500
# number of UpgradeReq MSHR miss cycles
@@ -223,10 +223,10 @@
system.cpu.l2cache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 #
number of cache copies performed
system.cpu.l2cache.demand_accesses 282272 #
number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52104.123006
# average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52103.272957
# average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000.874107
# average overall mshr miss latency
system.cpu.l2cache.demand_hits 95224 #
number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 9745972000 #
number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 9745813000 #
number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.662652 #
miss rate for demand accesses
system.cpu.l2cache.demand_misses 187048 #
number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
@@ -237,11 +237,11 @@
system.cpu.l2cache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 282272 #
number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52104.123006
# average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52103.272957
# average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000.874107
# average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 95224 #
number of overall hits
-system.cpu.l2cache.overall_miss_latency 9745972000 #
number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 9745813000 #
number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.662652 #
miss rate for overall accesses
system.cpu.l2cache.overall_misses 187048 #
number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 #
number of overall MSHR hits
@@ -253,16 +253,16 @@
system.cpu.l2cache.replacements 147733 #
number of replacements
system.cpu.l2cache.sampled_refs 172939 #
Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0
# number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18262.964194 #
Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 18262.944082 #
Cycle average of tags in use
system.cpu.l2cache.total_refs 110306 #
Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120636 #
number of writebacks
-system.cpu.numCycles 218461674 #
number of cpu cycles simulated
+system.cpu.numCycles 218420030 #
number of cpu cycles simulated
system.cpu.smtCommittedInsts 0 #
Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 #
Total number of cycles that the CPU was simultaneous multithreading.(SMT)
system.cpu.smt_cpi no_value #
CPI: Total SMT-CPI
system.cpu.smt_ipc no_value #
IPC: Total SMT-IPC
-system.cpu.threadCycles 218461674 #
Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 218420030 #
Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls 4583 #
Number of system calls
---------- End Simulation Statistics ----------
diff -r 20167772fb15 -r eae881827513
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini Thu Jul
02 23:23:06 2009 -0700
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini Sat Jul
04 21:46:23 2009 -0700
@@ -190,7 +190,7 @@
env=
errout=cerr
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