changeset ce086eca1ede in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ce086eca1ede
description:
ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that
were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
diffstat:
210 files changed, 12713 insertions(+), 8784 deletions(-)
src/mem/gems_common/std-includes.hh | 4
src/mem/gems_common/util.cc | 18
src/mem/gems_common/util.hh | 1
src/mem/protocol/MESI_CMP_directory-L1cache.sm | 51
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 7
src/mem/protocol/MESI_CMP_directory-mem.sm | 242 +
src/mem/protocol/MESI_CMP_directory-msg.sm | 32
src/mem/protocol/MESI_CMP_directory.slicc | 2
src/mem/protocol/MI_example-cache.sm | 51
src/mem/protocol/MI_example-dir.sm | 460 +++
src/mem/protocol/MI_example-dma.sm | 135 +
src/mem/protocol/MI_example-msg.sm | 32
src/mem/protocol/MI_example.slicc | 3
src/mem/protocol/RubySlicc_ComponentMapping.sm | 1
src/mem/protocol/RubySlicc_Exports.sm | 26
src/mem/protocol/RubySlicc_Types.sm | 58
src/mem/protocol/standard_1level_CMP-protocol.sm | 40
src/mem/ruby/buffers/MessageBuffer.cc | 14
src/mem/ruby/buffers/MessageBuffer.hh | 4
src/mem/ruby/common/Address.hh | 35
src/mem/ruby/common/Consumer.hh | 3
src/mem/ruby/common/DataBlock.cc | 95
src/mem/ruby/common/DataBlock.hh | 98
src/mem/ruby/common/Debug.cc | 68
src/mem/ruby/common/Debug.hh | 38
src/mem/ruby/common/Driver.hh | 19
src/mem/ruby/common/Global.hh | 25
src/mem/ruby/common/Set.cc | 7
src/mem/ruby/common/SubBlock.cc | 10
src/mem/ruby/common/SubBlock.hh | 15
src/mem/ruby/common/TypeDefines.hh | 23
src/mem/ruby/config/MI_example-homogeneous.rb | 64
src/mem/ruby/config/RubyConfig.cc | 254 +-
src/mem/ruby/config/RubyConfig.hh | 206 +
src/mem/ruby/config/cfg.rb | 751 +++++
src/mem/ruby/config/config.hh | 388 +--
src/mem/ruby/config/defaults.rb | 181 +
src/mem/ruby/config/libruby_cfg_test.cc | 14
src/mem/ruby/config/print_cfg.rb | 14
src/mem/ruby/config/rubyconfig.defaults | 68
src/mem/ruby/config/tester.defaults | 17
src/mem/ruby/eventqueue/RubyEventQueue.cc | 6
src/mem/ruby/filters/AbstractBloomFilter.hh | 71
src/mem/ruby/filters/BlockBloomFilter.cc | 147 +
src/mem/ruby/filters/BlockBloomFilter.hh | 82
src/mem/ruby/filters/BulkBloomFilter.cc | 232 +
src/mem/ruby/filters/BulkBloomFilter.hh | 87
src/mem/ruby/filters/GenericBloomFilter.cc | 150 +
src/mem/ruby/filters/GenericBloomFilter.hh | 94
src/mem/ruby/filters/H3BloomFilter.cc | 210 +
src/mem/ruby/filters/H3BloomFilter.hh | 1258
++++++++++
src/mem/ruby/filters/LSB_CountingBloomFilter.cc | 141 +
src/mem/ruby/filters/LSB_CountingBloomFilter.hh | 82
src/mem/ruby/filters/MultiBitSelBloomFilter.cc | 191 +
src/mem/ruby/filters/MultiBitSelBloomFilter.hh | 97
src/mem/ruby/filters/MultiGrainBloomFilter.cc | 172 +
src/mem/ruby/filters/MultiGrainBloomFilter.hh | 88
src/mem/ruby/filters/NonCountingBloomFilter.cc | 144 +
src/mem/ruby/filters/NonCountingBloomFilter.hh | 88
src/mem/ruby/init.cc | 191 -
src/mem/ruby/init.hh | 50
src/mem/ruby/libruby.cc | 206 +
src/mem/ruby/libruby.hh | 109
src/mem/ruby/libruby_internal.hh | 13
src/mem/ruby/network/Network.cc | 34
src/mem/ruby/network/Network.hh | 26
src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh | 2
src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc | 38
src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh | 15
src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc | 10
src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc | 11
src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh | 2
src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc | 7
src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh | 4
src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc | 4
src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc | 6
src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc | 2
src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc | 2
src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc | 47
src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh | 16
src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh | 79
src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc | 8
src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc | 4
src/mem/ruby/network/garnet-flexible-pipeline/Router.cc | 16
src/mem/ruby/network/simple/CustomTopology.cc | 140 +
src/mem/ruby/network/simple/CustomTopology.hh | 17
src/mem/ruby/network/simple/HierarchicalSwitchTopology.cc | 66
src/mem/ruby/network/simple/HierarchicalSwitchTopology.hh | 17
src/mem/ruby/network/simple/PerfectSwitch.cc | 12
src/mem/ruby/network/simple/PtToPtTopology.cc | 82
src/mem/ruby/network/simple/PtToPtTopology.hh | 17
src/mem/ruby/network/simple/SimpleNetwork.cc | 58
src/mem/ruby/network/simple/SimpleNetwork.hh | 8
src/mem/ruby/network/simple/Switch.cc | 5
src/mem/ruby/network/simple/Switch.hh | 2
src/mem/ruby/network/simple/Throttle.cc | 13
src/mem/ruby/network/simple/Throttle.hh | 5
src/mem/ruby/network/simple/Topology.cc | 489 ---
src/mem/ruby/network/simple/Topology.hh | 21
src/mem/ruby/network/simple/Torus2DTopology.cc | 84
src/mem/ruby/network/simple/Torus2DTopology.hh | 17
src/mem/ruby/profiler/AddressProfiler.cc | 21
src/mem/ruby/profiler/AddressProfiler.hh | 8
src/mem/ruby/profiler/Profiler.cc | 378 ++-
src/mem/ruby/profiler/Profiler.hh | 372 +-
src/mem/ruby/recorder/CacheRecorder.cc | 38
src/mem/ruby/recorder/CacheRecorder.hh | 4
src/mem/ruby/recorder/TraceRecord.cc | 41
src/mem/ruby/recorder/TraceRecord.hh | 11
src/mem/ruby/recorder/Tracer.cc | 41
src/mem/ruby/recorder/Tracer.hh | 14
src/mem/ruby/slicc_interface/AbstractCacheEntry.cc | 2
src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 3
src/mem/ruby/slicc_interface/AbstractChip.cc | 47
src/mem/ruby/slicc_interface/AbstractChip.hh | 126 -
src/mem/ruby/slicc_interface/AbstractController.hh | 33
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 285 --
src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc | 25
src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 29
src/mem/ruby/storebuffer/hfa.hh | 103
src/mem/ruby/storebuffer/hfatypes.hh | 80
src/mem/ruby/storebuffer/interface.cc | 67
src/mem/ruby/storebuffer/interface.hh | 46
src/mem/ruby/storebuffer/stb_interface.cc | 73
src/mem/ruby/storebuffer/stb_interface.hh | 42
src/mem/ruby/storebuffer/storebuffer.cc | 564 ++++
src/mem/ruby/storebuffer/storebuffer.hh | 150 +
src/mem/ruby/system/AbstractMemOrCache.hh | 1
src/mem/ruby/system/CacheMemory.hh | 395 +--
src/mem/ruby/system/DMASequencer.cc | 130 +
src/mem/ruby/system/DMASequencer.hh | 49
src/mem/ruby/system/DirectoryMemory.cc | 165 -
src/mem/ruby/system/DirectoryMemory.hh | 37
src/mem/ruby/system/MemoryControl.cc | 156 -
src/mem/ruby/system/MemoryControl.hh | 20
src/mem/ruby/system/MemoryVector.hh | 81
src/mem/ruby/system/NodePersistentTable.cc | 193 -
src/mem/ruby/system/NodePersistentTable.hh | 99
src/mem/ruby/system/PersistentArbiter.cc | 165 -
src/mem/ruby/system/PersistentArbiter.hh | 107
src/mem/ruby/system/PersistentTable.cc | 194 -
src/mem/ruby/system/PersistentTable.hh | 99
src/mem/ruby/system/ProcessorInterface.hh | 45
src/mem/ruby/system/RubyPort.cc | 5
src/mem/ruby/system/RubyPort.hh | 60
src/mem/ruby/system/Sequencer.cc | 1230
+++------
src/mem/ruby/system/Sequencer.hh | 98
src/mem/ruby/system/StoreBuffer.cc | 302 --
src/mem/ruby/system/StoreBuffer.hh | 121
src/mem/ruby/system/StoreCache.cc | 178 -
src/mem/ruby/system/StoreCache.hh | 85
src/mem/ruby/system/System.cc | 404 ++-
src/mem/ruby/system/System.hh | 134 -
src/mem/ruby/system/TBETable.hh | 21
src/mem/ruby/tester/BarrierGenerator.cc | 333 --
src/mem/ruby/tester/BarrierGenerator.hh | 138 -
src/mem/ruby/tester/Check.cc | 310 --
src/mem/ruby/tester/Check.hh | 107
src/mem/ruby/tester/CheckTable.cc | 128 -
src/mem/ruby/tester/CheckTable.hh | 93
src/mem/ruby/tester/DetermGETXGenerator.cc | 72
src/mem/ruby/tester/DetermGETXGenerator.hh | 17
src/mem/ruby/tester/DetermInvGenerator.cc | 100
src/mem/ruby/tester/DetermInvGenerator.hh | 11
src/mem/ruby/tester/DetermSeriesGETSGenerator.cc | 56
src/mem/ruby/tester/DetermSeriesGETSGenerator.hh | 11
src/mem/ruby/tester/DeterministicDriver.cc | 145 -
src/mem/ruby/tester/DeterministicDriver.hh | 50
src/mem/ruby/tester/Driver_Tester.cc | 44
src/mem/ruby/tester/Driver_Tester.hh | 82
src/mem/ruby/tester/EventQueue_Tester.hh | 118
src/mem/ruby/tester/Global_Tester.hh | 74
src/mem/ruby/tester/Instruction.cc | 51
src/mem/ruby/tester/Instruction.hh | 57
src/mem/ruby/tester/RaceyDriver.cc | 67
src/mem/ruby/tester/RaceyDriver.hh | 32
src/mem/ruby/tester/RaceyPseudoThread.cc | 353 ++
src/mem/ruby/tester/RaceyPseudoThread.hh | 151 +
src/mem/ruby/tester/RequestGenerator.cc | 220 -
src/mem/ruby/tester/RequestGenerator.hh | 102
src/mem/ruby/tester/SpecifiedGenerator.cc | 4
src/mem/ruby/tester/SpecifiedGenerator.hh | 8
src/mem/ruby/tester/SyntheticDriver.cc | 286 --
src/mem/ruby/tester/SyntheticDriver.hh | 118
src/mem/ruby/tester/Tester.cc | 112
src/mem/ruby/tester/Tester.hh | 93
src/mem/ruby/tester/main.cc | 9
src/mem/ruby/tester/main.hh | 9
src/mem/ruby/tester/test_framework.cc | 435 +--
src/mem/ruby/tester/test_framework.hh | 4
src/mem/slicc/ast/ASTs.hh | 1
src/mem/slicc/ast/EnqueueStatementAST.cc | 2
src/mem/slicc/ast/MachineAST.cc | 6
src/mem/slicc/ast/MachineAST.hh | 5
src/mem/slicc/ast/MethodCallExprAST.cc | 26
src/mem/slicc/ast/NewExprAST.cc | 9
src/mem/slicc/ast/NewExprAST.hh | 20
src/mem/slicc/ast/ObjDeclAST.cc | 29
src/mem/slicc/parser/lexer.ll | 9
src/mem/slicc/parser/parser.yy | 28
src/mem/slicc/symbols/Func.cc | 5
src/mem/slicc/symbols/Func.hh | 2
src/mem/slicc/symbols/StateMachine.cc | 439 +++
src/mem/slicc/symbols/StateMachine.hh | 34
src/mem/slicc/symbols/Symbol.hh | 4
src/mem/slicc/symbols/SymbolTable.cc | 731 -----
src/mem/slicc/symbols/SymbolTable.hh | 2
src/mem/slicc/symbols/Type.cc | 94
src/mem/slicc/symbols/Type.hh | 3
src/mem/slicc/symbols/Var.hh | 2
diffs (truncated from 27384 to 300 lines):
diff -r a63d1dc4c820 -r ce086eca1ede src/mem/gems_common/std-includes.hh
--- a/src/mem/gems_common/std-includes.hh Mon Jul 06 15:49:47 2009 -0700
+++ b/src/mem/gems_common/std-includes.hh Mon Jul 06 15:49:47 2009 -0700
@@ -26,6 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+/*
+ * $Id: std-includes.hh,v 3.7 2003/02/24 21:05:24 xu Exp $
+ */
+
#ifndef INCLUDES_H
#define INCLUDES_H
diff -r a63d1dc4c820 -r ce086eca1ede src/mem/gems_common/util.cc
--- a/src/mem/gems_common/util.cc Mon Jul 06 15:49:47 2009 -0700
+++ b/src/mem/gems_common/util.cc Mon Jul 06 15:49:47 2009 -0700
@@ -30,8 +30,7 @@
* $Id$
*/
-#include <cassert>
-
+#include "assert.hh"
#include "mem/gems_common/util.hh"
// Split a string into a head and tail strings on the specified
@@ -43,7 +42,7 @@
string head = "";
string tail = "";
- unsigned counter = 0;
+ uint counter = 0;
while(counter < str.size()) {
if (str[counter] == split_character) {
counter++;
@@ -91,6 +90,19 @@
return ret;
}
+bool string_to_bool(const string & str)
+{
+ string lower(str);
+ for (size_t i=0;i<str.length();i++)
+ lower[i] = tolower(str[i]);
+ if (lower == "true")
+ return true;
+ else if (lower == "false")
+ return false;
+ else
+ assert(0);
+}
+
// Log functions
int log_int(long long n)
{
diff -r a63d1dc4c820 -r ce086eca1ede src/mem/gems_common/util.hh
--- a/src/mem/gems_common/util.hh Mon Jul 06 15:49:47 2009 -0700
+++ b/src/mem/gems_common/util.hh Mon Jul 06 15:49:47 2009 -0700
@@ -39,6 +39,7 @@
string bool_to_string(bool value);
string int_to_string(int n, bool zero_fill = false, int width = 0);
float string_to_float(string& str);
+bool string_to_bool(const string & str);
int log_int(long long n);
bool is_power_of_2(long long n);
diff -r a63d1dc4c820 -r ce086eca1ede
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Mon Jul 06 15:49:47
2009 -0700
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Mon Jul 06 15:49:47
2009 -0700
@@ -33,7 +33,7 @@
*/
-machine(L1Cache, "MSI Directory L1 Cache CMP") {
+machine(L1Cache, "MSI Directory L1 Cache CMP") : LATENCY_L1_REQUEST_LATENCY
LATENCY_L1_RESPONSE_LATENCY LATENCY_TO_L2_LATENCY {
// NODE L1 CACHE
// From this node's L1 cache TO the network
@@ -136,12 +136,21 @@
TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
- CacheMemory L1IcacheMemory, template_hack="<L1Cache_Entry>",
constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1I"',
abstract_chip_ptr="true";
- CacheMemory L1DcacheMemory, template_hack="<L1Cache_Entry>",
constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1D"',
abstract_chip_ptr="true";
+// CacheMemory L1IcacheMemory, template_hack="<L1Cache_Entry>",
constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1I"',
abstract_chip_ptr="true";
+// CacheMemory L1DcacheMemory, template_hack="<L1Cache_Entry>",
constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1D"',
abstract_chip_ptr="true";
- MessageBuffer mandatoryQueue, ordered="false", rank="100",
abstract_chip_ptr="true";
+ CacheMemory L1IcacheMemory,
factory='RubySystem::getCache(m_cfg["L1Icache"])';
- Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
+ CacheMemory L1DcacheMemory,
factory='RubySystem::getCache(m_cfg["L1Dcache"])';
+
+
+// MessageBuffer mandatoryQueue, ordered="false", rank="100",
abstract_chip_ptr="true";
+
+// Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
+
+ MessageBuffer mandatoryQueue, ordered="false";
+ Sequencer sequencer, factory='RubySystem::getSequencer(m_cfg["sequencer"])';
+
int cache_state_to_int(State state);
@@ -290,40 +299,40 @@
// ** INSTRUCTION ACCESS ***
// Check to see if it is in the OTHER L1
- if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
+ if (L1DcacheMemory.isTagPresent(in_msg.LineAddress)) {
// The block is in the wrong L1, put the request on the queue to
the shared L2
- trigger(Event:L1_Replacement, in_msg.Address);
+ trigger(Event:L1_Replacement, in_msg.LineAddress);
}
- if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
+ if (L1IcacheMemory.isTagPresent(in_msg.LineAddress)) {
// The tag matches for the L1, so the L1 asks the L2 for it.
- trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.Address);
+ trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress);
} else {
- if (L1IcacheMemory.cacheAvail(in_msg.Address)) {
+ if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1
so let's see if the L2 has it
- trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.Address);
+ trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress);
} else {
// No room in the L1, so we need to make room in the L1
- trigger(Event:L1_Replacement,
L1IcacheMemory.cacheProbe(in_msg.Address));
+ trigger(Event:L1_Replacement,
L1IcacheMemory.cacheProbe(in_msg.LineAddress));
}
}
} else {
// *** DATA ACCESS ***
// Check to see if it is in the OTHER L1
- if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
+ if (L1IcacheMemory.isTagPresent(in_msg.LineAddress)) {
// The block is in the wrong L1, put the request on the queue to
the shared L2
- trigger(Event:L1_Replacement, in_msg.Address);
+ trigger(Event:L1_Replacement, in_msg.LineAddress);
}
- if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
+ if (L1DcacheMemory.isTagPresent(in_msg.LineAddress)) {
// The tag matches for the L1, so the L1 ask the L2 for it
- trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.Address);
+ trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress);
} else {
- if (L1DcacheMemory.cacheAvail(in_msg.Address)) {
+ if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1
let's see if the L2 has it
- trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.Address);
+ trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress);
} else {
// No room in the L1, so we need to make room in the L1
- trigger(Event:L1_Replacement,
L1DcacheMemory.cacheProbe(in_msg.Address));
+ trigger(Event:L1_Replacement,
L1DcacheMemory.cacheProbe(in_msg.LineAddress));
}
}
}
@@ -517,7 +526,7 @@
}
action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
- enqueue(unblockNetwork_out, ResponseMsg, latency="1") {
+ enqueue(unblockNetwork_out, ResponseMsg, latency="TO_L2_LATENCY") {
out_msg.Address := address;
out_msg.Type := CoherenceResponseType:UNBLOCK;
out_msg.Sender := machineID;
@@ -527,7 +536,7 @@
}
action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
- enqueue(unblockNetwork_out, ResponseMsg, latency="1") {
+ enqueue(unblockNetwork_out, ResponseMsg, latency="TO_L2_LATENCY") {
out_msg.Address := address;
out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
out_msg.Sender := machineID;
diff -r a63d1dc4c820 -r ce086eca1ede
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Mon Jul 06 15:49:47
2009 -0700
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Mon Jul 06 15:49:47
2009 -0700
@@ -156,9 +156,12 @@
bool isPresent(Address);
}
- TBETable L2_TBEs, template_hack="<L2Cache_TBE>";
+ TBETable L2_TBEs, template_hack="<L2Cache_TBE>", no_vector="true";
- CacheMemory L2cacheMemory, template_hack="<L2Cache_Entry>",
constructor_hack='L2_CACHE_NUM_SETS_BITS,L2_CACHE_ASSOC,MachineType_L2Cache,int_to_string(i)';
+// CacheMemory L2cacheMemory, template_hack="<L2Cache_Entry>",
constructor_hack='L2_CACHE_NUM_SETS_BITS,L2_CACHE_ASSOC,MachineType_L2Cache,int_to_string(i)';
+
+
+ CacheMemory L2cacheMemory, factory='RubySystem::getCache(m_cfg["cache"])',
no_vector="true";
// inclusive cache, returns L2 entries only
Entry getL2CacheEntry(Address addr), return_by_ref="yes" {
diff -r a63d1dc4c820 -r ce086eca1ede src/mem/protocol/MESI_CMP_directory-mem.sm
--- a/src/mem/protocol/MESI_CMP_directory-mem.sm Mon Jul 06 15:49:47
2009 -0700
+++ b/src/mem/protocol/MESI_CMP_directory-mem.sm Mon Jul 06 15:49:47
2009 -0700
@@ -31,23 +31,39 @@
* $Id: MOESI_CMP_token-dir.sm 1.6 05/01/19 15:48:35-06:00
[email protected] $
*/
+// This file is copied from Yasuko Watanabe's prefetch / memory protocol
+// Copied here by aep 12/14/07
-machine(Directory, "Token protocol") {
+
+machine(Directory, "MESI_CMP_filter_directory protocol") :
LATENCY_MEMORY_LATENCY LATENCY_TO_MEM_CTRL_LATENCY {
MessageBuffer requestToDir, network="From", virtual_network="2",
ordered="false";
MessageBuffer responseToDir, network="From", virtual_network="3",
ordered="false";
MessageBuffer responseFromDir, network="To", virtual_network="3",
ordered="false";
+ MessageBuffer dmaRequestFromDir, network="To", virtual_network="4",
ordered="true", no_vector="true";
+ MessageBuffer dmaRequestToDir, network="From", virtual_network="5",
ordered="true", no_vector="true";
+
+
// STATES
enumeration(State, desc="Directory states", default="Directory_State_I") {
// Base states
I, desc="Owner";
+ ID, desc="Intermediate state for DMA_READ when in I";
+ ID_W, desc="Intermediate state for DMA_WRITE when in I";
}
// Events
enumeration(Event, desc="Directory events") {
- Fetch, desc="A GETX arrives";
- Data, desc="A GETS arrives";
+ Fetch, desc="A memory fetch arrives";
+ Data, desc="writeback data arrives";
+ Memory_Data, desc="Fetched data from memory arrives";
+ Memory_Ack, desc="Writeback Ack from memory arrives";
+//added by SS for dma
+ DMA_READ, desc="A DMA Read memory request";
+ DMA_WRITE, desc="A DMA Write memory request";
+
+
}
// TYPES
@@ -62,10 +78,21 @@
bool isPresent(Address);
}
+ // to simulate detailed DRAM
+ external_type(MemoryControl, inport="yes", outport="yes") {
+
+ }
+
// ** OBJECTS **
- DirectoryMemory directory, constructor_hack="i";
+// DirectoryMemory directory, constructor_hack="i";
+// MemoryControl memBuffer, constructor_hack="i";
+
+ DirectoryMemory directory,
factory='RubySystem::getDirectory(m_cfg["directory_name"])';
+
+ MemoryControl memBuffer,
factory='RubySystem::getMemoryControl(m_cfg["memory_controller_name"])';
+
State getState(Address addr) {
return State:I;
@@ -74,20 +101,44 @@
void setState(Address addr, State state) {
}
+ bool isGETRequest(CoherenceRequestType type) {
+ return (type == CoherenceRequestType:GETS) ||
+ (type == CoherenceRequestType:GET_INSTR) ||
+ (type == CoherenceRequestType:GETX);
+ }
+
+
// ** OUT_PORTS **
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
+ out_port(memQueue_out, MemoryMsg, memBuffer);
+ out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaRequestFromDir);
// ** IN_PORTS **
+//added by SS for dma
+ in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
+ if (dmaRequestQueue_in.isReady()) {
+ peek(dmaRequestQueue_in, DMARequestMsg) {
+ if (in_msg.Type == DMARequestType:READ) {
+ trigger(Event:DMA_READ, in_msg.PhysicalAddress);
+ } else if (in_msg.Type == DMARequestType:WRITE) {
+ trigger(Event:DMA_WRITE, in_msg.PhysicalAddress);
+ } else {
+ error("Invalid message");
+ }
+ }
+ }
+ }
+
+
in_port(requestNetwork_in, RequestMsg, requestToDir) {
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
