You seem to have broken se.py for cases where you're not using the detailed CPU. In those cases, "workloads" isn't defined and python barfs on the line where you try to check its length. One potential fix is to set workloads to "None" before "if options.detailed:" and then wrap the new line you added with "if workloads is not None:". That seems to work for the non-detailed case, but if you don't mind I'll leave the testing/committing up to you.
Gabe Korey Sewell wrote: > changeset c9f811e3def9 in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=c9f811e3def9 > description: > merge sparc fix w/2t regress fix > > diffstat: > > 1 file changed, 2 insertions(+), 2 deletions(-) > src/arch/sparc/nativetrace.cc | 4 ++-- > > diffs (21 lines): > > diff -r 2352ea7fb955 -r c9f811e3def9 src/arch/sparc/nativetrace.cc > --- a/src/arch/sparc/nativetrace.cc Sat Jul 25 22:22:13 2009 -0400 > +++ b/src/arch/sparc/nativetrace.cc Sat Jul 25 22:24:45 2009 -0400 > @@ -36,7 +36,7 @@ > > namespace Trace { > > -static char *intRegNames[SparcISA::NumIntArchRegs] = { > +static const char *intRegNames[SparcISA::NumIntArchRegs] = { > //Global registers > "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", > //Output registers > @@ -58,7 +58,7 @@ > > // I doubt a real SPARC will describe more integer registers than this. > assert(SparcISA::NumIntArchRegs == 32); > - char **regName = intRegNames; > + const char **regName = intRegNames; > for (int i = 0; i < SparcISA::NumIntArchRegs; i++) { > regVal = tc->readIntReg(i); > read(&realRegVal, sizeof(realRegVal)); > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
