changeset 1895318a1b26 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1895318a1b26
description:
ARM: Handle register indexed system calls.
diffstat:
3 files changed, 7 insertions(+), 2 deletions(-)
src/arch/arm/isa/decoder.isa | 5 ++++-
src/arch/arm/isa/operands.isa | 1 +
src/arch/arm/linux/process.cc | 3 ++-
diffs (39 lines):
diff -r 9345de6fca33 -r 1895318a1b26 src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Mon Jul 27 00:50:55 2009 -0700
+++ b/src/arch/arm/isa/decoder.isa Mon Jul 27 00:51:01 2009 -0700
@@ -422,7 +422,10 @@
// ARM System Call (SoftWare Interrupt)
1: swi({{ if (testPredicate(Cpsr, condCode))
{
- xc->syscall(IMMED_23_0);
+ if (IMMED_23_0)
+ xc->syscall(IMMED_23_0);
+ else
+ xc->syscall(R7);
}
}});
}
diff -r 9345de6fca33 -r 1895318a1b26 src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Mon Jul 27 00:50:55 2009 -0700
+++ b/src/arch/arm/isa/operands.isa Mon Jul 27 00:51:01 2009 -0700
@@ -57,6 +57,7 @@
'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
+ 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
#Destination register for load/store double instructions
'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead,
maybePCWrite),
diff -r 9345de6fca33 -r 1895318a1b26 src/arch/arm/linux/process.cc
--- a/src/arch/arm/linux/process.cc Mon Jul 27 00:50:55 2009 -0700
+++ b/src/arch/arm/linux/process.cc Mon Jul 27 00:51:01 2009 -0700
@@ -448,7 +448,8 @@
// Angel SWI syscalls are unsupported in this release
if (callnum == 0x123456) {
panic("Attempt to execute an ANGEL_SWI system call (newlib-related)");
- } else if ((callnum & 0x00f00000) == 0x00900000) {
+ } else if ((callnum & 0x00f00000) == 0x00900000 ||
+ (callnum & 0xf0000) == 0xf0000) {
callnum &= 0x000fffff;
if ((callnum & 0x0f0000) == 0xf0000) {
callnum -= 0x0f0001;
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