changeset 2f551f287dd0 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=2f551f287dd0 description: ARM: Update the reference outputs for the new binary and fstat64 struct.
diffstat: 2 files changed, 15 insertions(+), 15 deletions(-) tests/quick/00.hello/ref/arm/linux/simple-atomic/simout | 8 ++-- tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt | 22 ++++++------ diffs (59 lines): diff -r 05f1d2cd7e9e -r 2f551f287dd0 tests/quick/00.hello/ref/arm/linux/simple-atomic/simout --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout Mon Jul 27 00:51:20 2009 -0700 +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout Mon Jul 27 00:51:27 2009 -0700 @@ -5,13 +5,13 @@ All Rights Reserved -M5 compiled Jun 9 2009 23:46:33 -M5 revision 6639f3c716a6 6238 default qtip tip armreg.patch qbase -M5 started Jun 9 2009 23:53:49 +M5 compiled Jul 26 2009 15:06:04 +M5 revision e7266157d0ed 6396 default qtip tip hellostatupdate.patch +M5 started Jul 26 2009 15:06:04 M5 executing on fajita command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 2299000 because target called exit() +Exiting @ tick 2637000 because target called exit() diff -r 05f1d2cd7e9e -r 2f551f287dd0 tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt Mon Jul 27 00:51:20 2009 -0700 +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt Mon Jul 27 00:51:27 2009 -0700 @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 79163 # Simulator instruction rate (inst/s) -host_mem_usage 189980 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 39442081 # Simulator tick rate (ticks/s) +host_inst_rate 9693 # Simulator instruction rate (inst/s) +host_mem_usage 189748 # Number of bytes of host memory used +host_seconds 0.54 # Real time elapsed on the host +host_tick_rate 4842984 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4598 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2299000 # Number of ticks simulated +sim_insts 5274 # Number of instructions simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2637000 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -28,9 +28,9 @@ system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4599 # number of cpu cycles simulated -system.cpu.num_insts 4598 # Number of instructions executed -system.cpu.num_refs 1851 # Number of memory references -system.cpu.workload.PROG:num_syscalls 14 # Number of system calls +system.cpu.numCycles 5275 # number of cpu cycles simulated +system.cpu.num_insts 5274 # Number of instructions executed +system.cpu.num_refs 2057 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
