changeset c3372644e033 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c3372644e033
description:
ARM: Add in spots for the VFP control registers.
diffstat:
2 files changed, 8 insertions(+), 2 deletions(-)
src/arch/arm/isa/operands.isa | 7 +++++--
src/arch/arm/miscregs.hh | 3 +++
diffs (29 lines):
diff -r 302dbd16c404 -r c3372644e033 src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Mon Jul 27 00:52:59 2009 -0700
+++ b/src/arch/arm/isa/operands.isa Mon Jul 27 00:53:10 2009 -0700
@@ -82,7 +82,10 @@
'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
- 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42),
- 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43),
+ 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42),
+ 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43),
+ 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44),
+ 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45),
+ 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46)
}};
diff -r 302dbd16c404 -r c3372644e033 src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Mon Jul 27 00:52:59 2009 -0700
+++ b/src/arch/arm/miscregs.hh Mon Jul 27 00:53:10 2009 -0700
@@ -62,6 +62,9 @@
MISCREG_SPSR_UND,
MISCREG_SPSR_ABT,
MISCREG_FPSR,
+ MISCREG_FPSID,
+ MISCREG_FPSCR,
+ MISCREG_FPEXC,
NUM_MISCREGS
};
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